An Efficient FEC Encoder Core for VCM LEO Satellite-Ground Communications

Abstract

A powerful forward error correction (FEC) scheme based on the serial concatenation of Bose-Chaudhuri-Hocquenghen (BCH) and low-density parity-check (LDPC) codes has been adopted by the second generation digital video broadcast (DVB-S2) standard due to their near Shannon limit performance. This paper proposes an efficient FEC encoder core to support different DVB-S2 codes for variable coding modulation (VCM) schemes of low earth orbit (LEO) satellite-ground communications. By exploring the properties of different concatenated BCH-LDPC codes and reusing the computation units and memories, the compatibility is achieved and the utilization of hardware resources is improved. Besides, parallel computing is performed to speed up the acquisition of check bits, which allows the encoding throughput to be increased. Hardware architecture implementation on Xilinx XC7K325t field programmable gate array (FPGA) shows that the encoding throughput rate of the proposed FEC encoder core can reach 1.19 Gb/s. And the overall data throughput is improved by 30.9% compared with the constant coding modulation (CCM) schemes.

Design and implementation of variable coding and modulation for LEO high‐resolution Earth observation satellite

“…Table 3 shows the FPGA implementation results and the corresponding resource usage of the five rates compatible DVB‐S2 LDPC encoder designed in this paper. To show its improvements and advantages, we compare them with the implementation results of the latest literature presented in previous studies 14–16 . The encoder structure in Zinchenko et al 14 can support a variety of code rates, but due to the serial coding architecture, its throughput of each code rate encoder is low.…”

“…The encoder implementation method in Lazarenko 15 can support all code rates and frame types of DVB‐S2 but does neither consider the scenario of dynamic adjustable throughput nor the optimization of the high‐throughput design. The encoder in Kang et al 16 adopts two code rates realized by Xilinx FPGA XC7K325t and can achieve a throughput of 1.19 Gbps when the clock frequency is 389.5 MHz.…”

“…To show its improvements and advantages, we compare them with the implementation results of the latest literature presented in previous studies. [14][15][16] The encoder structure in Zinchenko et al 14 can support a variety of code rates, but due to the serial coding architecture, its throughput of each code rate encoder is low. The encoder implementation method in Lazarenko 15 can support all code rates and frame types of DVB-S2 but does neither consider the scenario of dynamic adjustable throughput nor the optimization of the high-throughput design.…”

An LDPC Encoder Architecture With Up to 47.5 Gbps Throughput for DVB-S2/S2X Standards

“…In terms of encoding, the Partitioned H method is particularly well suited for this type of LDPC code, but the multiplication of the information sequence and a largedimensional sparse matrix involved in the method is related to the complexity of the encoder implementation and is also the main source of encoding delay. To accomplish this step, the encoder architectures proposed in [14]- [19] use the processing method of computing and updating sub-matrix sequentially, Random Access Memories (RAMs) are used for storage of computation results and parameters of the parity-check matrix. In addition, some logic is required for state control and barrel shift.…”

Design and Implementation of a DVB-S2 Reconfigurable Datapath BCH Encoder for High Data-Rate Payload Data Telemetry

“…• Such configurability provides increased flexibility to potential users, compared to state-of-the-art examples of full DVB-S2 compliant encoders supporting all CCM, VCM and ACM modes (i.e. [7], [8] and [9]), remaining competitive in terms of performances. The rest of this paper is organized as follows.…”