An LDPC Encoder Architecture With Up to 47.5 Gbps Throughput for DVB-S2/S2X Standards

Abstract

Date of publication xxxx 00, 0000, date of current version xxxx 00, 0000.

An efficient GC-LDPC encoder architecture for high-speed NAND flash applications

“…This would lead to an excess of encoding cycles. Thus, to improve the computing capacity of the SRAA unit in each cycle, we expand a single dense multiplication in (10). Here, the 1 × 𝑍 bit sequence is denoted by 𝛼 = [𝑎 1 , 𝑎 2 , ..., 𝑎 𝑍 ], the 𝑍 × 𝑍 dense matrix is denoted by 𝛽, and 𝑏 𝑙 (𝑍 ) denotes the first row of 𝛽 that cyclic shifted to the left by 𝑍 bits.…”

“…(10) In (10), a single dense multiplication consists of similar 𝑍 operations. Each operation consists of one multiplication, one addition, and one cyclic shift left.…”

“…By extracting common subexpressions, encoder architectures can be efficiently implemented as merged gate-level circuits in several standards, such as IEEE 802.11n [6,7,8]. In other standards, optimizing the computing unit for dense multiplications can reduce the computing resource overhead of the architecture [9,10,11]. In contrast, other classical encoder architectures can be applied to more types of LDPC codes.…”