FPGA Implementation of ECT Digital System for Imaging Conductive Materials

Deabes, Wael

doi:10.3390/a12020028

Cited by 6 publications

(7 citation statements)

References 26 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In [66], a complete standalone 2D ECT system (16x16 frame size) using FPGA (Cyclone-V) was suggested. The system, which hosts the LBP algorithm, was designed for imaging lost foam coating process.…”

Section: A Recent Reviewmentioning

confidence: 99%

Electrical Tomography Hardware Systems for Real-Time Applications: a Review

et al. 2022

View full text Add to dashboard Cite

This paper presents a review of two-dimensional (2D) and three-dimensional (3D) electrical tomography (ET) hardware accelerators for real-time applications. While many recent review papers have discussed various algorithms for image reconstruction or acquisition systems, none of them has considered state-of-the-art hardware implementations of the associated image reconstruction algorithms to achieve real-time performance, especially for 3D ET where the computation requirement is excessively high. A 3D ET is useful in various applications such as robotics, autonomous vehicles, and process control, but it is computationally very expensive with respect to its 2D counterpart. Most implementations are based on single or multi-core CPUs and, to a lesser extent, on either graphics processing units (GPUs) or field programmable gate arrays (FPGAs). However, there is a clear gap between the currently available processors, whose computation power exceeds hundreds of teraflops per second (TOPS) at a reasonable low power consumption, and the ones recently used in ET systems. This gives great potential for nextgeneration ET systems to achieve real-time 2D and 3D ET reconstruction within a small form factor. The paper summarizes the most recent ET hardware systems with respect to their performance in terms of quality and processing frame rate, reconstruction methods, along with optimization and future directions.

show abstract

Section: A Recent Reviewmentioning

confidence: 99%

Electrical Tomography Hardware Systems for Real-Time Applications: a Review

et al. 2022

View full text Add to dashboard Cite

show abstract

“…The method generates double BCD (Binary-Coded Decimal) numbers using decimal multiples 2X, 4X, and 5X. The redundant decimal adder is used to reduce the generated 2n BCD partial products to a redundant number in the range of [0,15]. The final redundant product is then converted to BCD encoding.…”

Section: Related Workmentioning

confidence: 99%

“…Since the set of applications taking advantage of these specialized units is somehow limited, most processors only include some kind of specific instructions to help in the execution of decimal operations performed in software. In this scenario, FPGAs (Field Programmable Gate Array) may be a good alternative for the execution of decimal arithmetic with dedicated hardware modules, like in many other applications [14,15]. Many financial applications already use FPGAs to speed-up the execution of their algorithms and so an hardware reprogrammable platform is already available.…”

Section: Introductionmentioning

confidence: 99%

Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor

Véstias

Neto

2021

Algorithms

View full text Add to dashboard Cite

Financial and commercial data are mostly represented in decimal format. To avoid errors introduced when converting some decimal fractions to binary, these data are processed with decimal arithmetic. Most processors only have hardwired binary arithmetic units. So, decimal operations are executed with slow software-based decimal arithmetic functions. For the fast execution of decimal operations, dedicated hardware units have been proposed and designed in FPGA. Decimal multiplication is found in most decimal-based applications and so its optimized design is very important for fast execution. In this paper two new parallel decimal multipliers in FPGA are proposed. These are based on a new decimal adder/subtractor also proposed in this paper. The new decimal multipliers improve state-of-the-art parallel decimal multipliers. Compared to previous architectures, implementation results show that the proposed multipliers achieve 26% better area and 12% better performance. Also, the new decimal multipliers reduce the area and performance gap to binary multipliers and are smaller for 32 digit operands.

show abstract

“…The FPGA realization of the matrix-vector multiplication algorithm has been tackled by many research work at the algorithmic level as well as at the bit-manipulation level [30][31][32]. Most of the FPGA implementation of these proposed parallel structure of the matrix multiplication at an algorithmic level are for small matrix dimensions.…”

Section: Introductionmentioning

confidence: 99%

Model-Based Hardware-Software Codesign of ECT Digital Processing Unit

Allam

Deabes

2021

Modelling and Simulation in Engineering

Self Cite

View full text Add to dashboard Cite

Image reconstruction algorithm and its controller constitute the main modules of the electrical capacitance tomography (ECT) system; in order to achieve the trade-off between the attainable performance and the flexibility of the image reconstruction and control design of the ECT system, hardware-software codesign of a digital processing unit (DPU) targeting FPGA system-on-chip (SoC) is presented. Design and implementation of software and hardware components of the ECT-DPU and their integration and verification based on the model-based design (MBD) paradigm are proposed. The inner-product of large vectors constitutes the core of the majority of these ECT image reconstruction algorithms. Full parallel implementation of large vector multiplication on FPGA consumes a huge number of resources and incurs long combinational path delay. The proposed MBD of the ECT-DPU tackles this problem by crafting a parametric segmented parallel inner-product architecture so as to work as the shared hardware core unit for the parallel matrix multiplication in the image reconstruction and control of the ECT system. This allowed the parameterized core unit to be configured at system-level to tackle large matrices with the segment length working as a design degree of freedom. It allows the trade-off between performance and resource usage and determines the level of computation parallelism. Using MBD with the proposed segmented architecture, the system design can be flexibly tailored to the designer specifications to fulfill the required performance while meeting the resources constraint. In the linear-back projection image reconstruction algorithm, the segmentation scheme has exhibited high resource saving of 43% and 71% for a small degradation in a frame rate of 3% and 14%, respectively.

show abstract

FPGA Implementation of ECT Digital System for Imaging Conductive Materials

Cited by 6 publications

References 26 publications

Electrical Tomography Hardware Systems for Real-Time Applications: a Review

Electrical Tomography Hardware Systems for Real-Time Applications: a Review

Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor

Model-Based Hardware-Software Codesign of ECT Digital Processing Unit

Contact Info

Product

Resources

About