Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor

Abstract

Financial and commercial data are mostly represented in decimal format. To avoid errors introduced when converting some decimal fractions to binary, these data are processed with decimal arithmetic. Most processors only have hardwired binary arithmetic units. So, decimal operations are executed with slow software-based decimal arithmetic functions. For the fast execution of decimal operations, dedicated hardware units have been proposed and designed in FPGA. Decimal multiplication is found in most decimal-based applications and so its optimized design is very important for fast execution. In this paper two new parallel decimal multipliers in FPGA are proposed. These are based on a new decimal adder/subtractor also proposed in this paper. The new decimal multipliers improve state-of-the-art parallel decimal multipliers. Compared to previous architectures, implementation results show that the proposed multipliers achieve 26% better area and 12% better performance. Also, the new decimal multipliers reduce the area and performance gap to binary multipliers and are smaller for 32 digit operands.

Design and Implementation of 12-Bit Arithmetic Logic Unit with 8 Operation Codes to Field Programmable Gate Array

“…The 12-bit multiplier will have two 12-bit inputs, 𝐴 and 𝐵, and one 24-bit output, and its schematic is developed based on the multiplication operation algorithm [21]. The AND gate is tasked to carry out the multiplication to each bit, and the 12-bit adder is tasked to sum the result of the multiplication [22]- [24]. The block diagram and the schematic of the 12-bit multiplier are depicted in Figure 2 and Figure 3.…”