FPGA Implementation of a Reed-Solomon CODEC for OTN G.709 Standard with Reduced Decoder Area

Barbosa, Tiago Campolina; Moreno, Robson Luiz; Pereira, Tales C.; Ferreira, Luís H. C.

doi:10.1109/wicom.2010.5600886

Cited by 5 publications

(4 citation statements)

References 9 publications

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“…(13) as 1116.9kHz. The error coding mechanism advantage is the introduction of the redundancy to the transmitted data for correcting the errors in the receiver path for further processing [9]. Reed Solomon (R-S) code are one of the error correcting codes belong to the family of non-binary cyclic error correcting codes and are employed for burst error correction.…”

Section: Concept Of Bit Error Rate (Ber)mentioning

confidence: 99%

Link Margin for Wireless Radio Communication Link

Singh¹,

Nirmal²,

Sharma³

2017

IJCT

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The systematic evaluation of the link budget calculation for the satellite and terrestrial communication is presented in this article. Communication link between the satellite and earth station is dependent on various propagation and associated losses which are either constant or vary with weather conditions. Role of receiver noise, antenna pointing mechanism, atmospheric effects, slant height, interferences, bit error rate on the link margin are detailed in this article. Various equations for link budget calculation and a comparative table at various frequency bands are shown in this article which is useful for predicting link margin of LEO, GEO and Deep space missions. Tele-command, telemetry and ranging link margin at various frequencies are presented and budget analysis at Ka-band frequency performed.

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Section: Concept Of Bit Error Rate (Ber)mentioning

confidence: 99%

Link Margin for Wireless Radio Communication Link

Singh¹,

Nirmal²,

Sharma³

2017

IJCT

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“…These days, communication system is often implemented on FPGA for lower development costs and its re-configurability [13]. RS decoders for several communication systems have been implemented on FPGA [14], [15]. However because FPGA is vulnerable to soft error, soft error tolerant system design is important for communication systems on FPGA [16].…”

Section: Related Workmentioning

confidence: 99%

An Analysis of Time Domain Reed Solomon Decoder with FPGA Implementation

Kato

Choomchuay

2017

IEICE Trans. Inf. & Syst.

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This paper analyzes the time domain Reed Solomon Decoder with FPGA implementation. Data throughput and area is carefully evaluated compared with typical frequency domain Reed Solomon Decoder. In this analysis, three hardware architecture to enhance the data throughput, namely, the pipelined architecture, the parallel architecture, and the truncated arrays, is evaluated, too. The evaluation reveals that the number of the consumed resources of RS (255, 239) is about 20% smaller than those of the frequency domain decoder although data throughput is less than 10% of the frequency domain decoder. The number of the consumed resources of the pipelined architecture is 28% smaller than that of the parallel architecture when data throughput is same. It is because the pipeline architecture requires less extra logics than the parallel architecture. To get higher data throughput, the pipelined architecture is better than the parallel architecture from the viewpoint of consumed resources.

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“…The GF is implemented according to a primitive polynomial. The polynomial must be primitive, so that all of its roots are primitive elements [9].…”

Section: Rs Code and Pgz Reviewmentioning

confidence: 99%

“…(2) [9], so the roots of the generator polynomial must also be the roots of the codeword. The polynomial p(x) is the remainder of the division between x n−k m(x) and g(x).…”

Section: A Encodingmentioning

confidence: 99%

A Reed-Solomon architecture for soft-core implementation

Ferreira

Moreno

et al. 2011

2011 International Symposium on Integrated Circuits

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This work presents a Reed-Solomon architecture for soft-core implementation, which is able to provide a robust communication in noisy links. It offers low power consumption by using a software oriented implementation in PicoBlaze that also reduces the used area of the logical device in FPGA. The implementation improves the BER performance and thus increase the communication range (up to 50%) and can be used in applications such as remote monitoring Wireless Sensor Network (up to 15% in noisy indoors) and medical applications (up to 31% in indoors with BER = 10 −7 ).

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FPGA Implementation of a Reed-Solomon CODEC for OTN G.709 Standard with Reduced Decoder Area

Cited by 5 publications

References 9 publications

Link Margin for Wireless Radio Communication Link

Link Margin for Wireless Radio Communication Link

An Analysis of Time Domain Reed Solomon Decoder with FPGA Implementation

A Reed-Solomon architecture for soft-core implementation

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