FPGA Implementation of a Memory-Efficient Hough Parameter Space for the Detection of Lines

Northcote, David; Crockett, Louise H.; Murray, Paul

doi:10.1109/iscas.2018.8351115

Cited by 5 publications

(3 citation statements)

References 12 publications

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“…Authors in the study [6] implement the Hough space using (Y-intercept, θ) and require 6.9% LUTs, 5.6% memory, and 15.54% slices without using DSP. Additionally, 5.18% LUTs, 9.34% slices, and 3.71% FF of resources are utilized in [7]. This system uses a significant number of resources for BRAM, at 66.67%.…”

Section: A Synthesized Resultsmentioning

confidence: 99%

“…The Angular Regions -Line Hough Transform (AR-LHT) method, based on techniques from LHT, is a memory-efficient approach for line detection in images. Utilizing the Hough Parameter Space (HPS) with minimal dispersion reduces memory usage significantly, as reported in [7]. Authors employ two smaller memories: a 1-bit Bitmap Region (RBM) and a downsized HPS.…”

Section: Introductionmentioning

confidence: 99%

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An Efficiency Hardware Design for Lane Detector Systems

Lam

2024

IJACSA

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The Hough Transform (HT) algorithm is a popular method for lane detection based on the 'voting' process to extract complete lines. The voting process is derived from the HT algorithm and then executed in parameter space (ρ, θ) to identify the 'votes' with the highest count, meaning that image points with pairs of angle θ and distance ρ corresponding to those 'votes' lie on the same line. However, this algorithm requires significant memory and computational complexity. In this paper, we propose a new algorithm for the Hough Space (HS) by utilizing parameterization (Y-intercept, θ) instead of (ρ, θ) parameterization and lane direction. This simplifies the inverse LHT operation and reduces the accumulator's size and computational complexity compared to the standard LHT. We aim to minimize processing time per frame for real-time processing. Our implementation operates at a frequency of 250MHz, and the processing time for each frame with a resolution of 1024x1024 is 4.19ms, achieving an accuracy of 85.49%. This design is synthesized on the Virtex-7 VC707 FPGA.

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Section: A Synthesized Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An Efficiency Hardware Design for Lane Detector Systems

Lam

2024

IJACSA

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“…The degree resolution is 1 degree between angles, hence 180 such processing elements are needed to compute for 180 degrees range. The result of each processing element is accumulated and stored in memory [6].…”

Section: Hough Transform Fpga Implementationmentioning

confidence: 99%

Hardware Acceleration of Lane Detection Algorithm: A GPU Versus FPGA Comparison

Alshemi¹,

Saif²,

Taher³

2022

Signal Processing and Vision

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A Complete Computer vision system can be divided into two main categories: detection and classification. The Lane detection algorithm is a part of the computer vision detection category and has been applied in autonomous driving and smart vehicle systems. The lane detection system is responsible for lane marking in a complex road environment. At the same time, lane detection plays a crucial role in the warning system for a car when departs the lane. The implemented lane detection algorithm is mainly divided into two steps: edge detection and line detection. In this paper, we will compare the state-of-the-art implementation performance obtained with both FPGA and GPU to evaluate the trade-off for latency, power consumption, and utilization. Our comparison emphasises the advantages and disadvantages of the two systems.

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