FPGA Hardware Implementation of DOA Estimation Algorithm Employing LU Decomposition

Hussain, Ahmed; Tayem, Nizar; Butt, Muhammad Omair; Soliman, Abdel-Hamid; Alhamed, Abdulrahman; Alshebeili, Saleh

doi:10.1109/access.2018.2820122

Cited by 26 publications

(25 citation statements)

References 19 publications

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“…However, it offers a slightly higher accuracy of 0.3°while consuming considerably high resources. A LU(Lower-Upper) factorization based technique is presented in [29]. The implemented technique performs LU factorization of the covariance matrix of the input signal before performing EVD.…”

Section: Related Workmentioning

confidence: 99%

“…LU factorization performed on 4 element ULA(Uniform Linear Array) leads to reduce the utilized FPGA resources, but still it does not satisfy the real-time requirement of pulse density. Among all presented algorithms in [29] LU-L(Lower-Upper factorization -Lower Triangle Matrix) is the most computationally efficient. It requires 3.95µ sec at 40 MHz for DoA estimation that enables to process 0.254 MPPS.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Towards Low Latency and Resource-Efficient FPGA Implementations of the MUSIC Algorithm for Direction of Arrival Estimation

Butt

Khan

Ullah

et al. 2021

IEEE Trans. Circuits Syst. I

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The estimation of the Direction of Arrival (DoA) is one of the most critical parameters for target recognition, identification and classification. MUltiple SIgnal Classification (MUSIC) is a powerful technique for DoA estimation. The algorithm requires complex mathematical operations like the computation of the covariance matrix for the input signals, eigenvalue decomposition and signal peak search. All these signal processing operations make real-time and resource-efficient implementation of the MUSIC algorithm on Field Programmable Gate Arrays (FPGAs) a challenge.In this paper, a novel design approach is proposed for the FPGAimplementation of the MUSIC algorithm. This approach enables a significant reduction in both FPGA resources and latency. In more detail, the proposed design enables the estimation of DoA in real-time scenarios in 2µsec with 30% to 50% fewer resources as compared to existing techniques.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Towards Low Latency and Resource-Efficient FPGA Implementations of the MUSIC Algorithm for Direction of Arrival Estimation

Butt

Khan

Ullah

et al. 2021

IEEE Trans. Circuits Syst. I

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show abstract

“…Regarding the hardware design efficiency of the proposed work, our literature survey cannot identify any other work with chip design. However, there have been works [28][29][30][31] with hardware implementations reported in recent years and all of them are using the FPGA technology. In industry practices, FPGA is usually employed in the cases of system prototyping or when product volume is not large enough to economically justify the Application Specific Integrated Circuit (ASIC) implementation.…”

Section: Comparison With Other Doa Hardware Implementation Workmentioning

confidence: 99%

“…This latency includes both the time spent in auto-correlation matrix calculation and the time to perform DoA estimation. From Table 6, designs [28,30,31] all can accomplish the estimation in less than 220 clock cycles. This is because they work on a smaller antenna array.…”

Section: Comparison With Other Doa Hardware Implementation Workmentioning

confidence: 99%

A Low Complexity, High Throughput DoA Estimation Chip Design for Adaptive Beamforming

Chen

Ma²,

Hwang

et al. 2020

Electronics

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Direction of Arrival (DoA) estimation is essential to adaptive beamforming widely used in many radar and wireless communication systems. Although many estimation algorithms have been investigated, most of them focus on the performance enhancement aspect but overlook the computing complexity or the hardware implementation issues. In this paper, a low-complexity yet effective DoA estimation algorithm and the corresponding hardware accelerator chip design are presented. The proposed algorithm features a combination of signal sub-space projection and parallel matching pursuit techniques, i.e., applying signal projection first before performing matching pursuit from a codebook. This measure helps minimize the interference from noise sub-space and makes the matching process free of extra orthogonalization computations. The computing complexity can thus be reduced significantly. In addition, estimations of all signal sources can be performed in parallel without going through a successive update process. To facilitate an efficient hardware implementation, the computing scheme of the estimation algorithm is also optimized. The most critical part of the algorithm, i.e., calculating the projection matrix, is largely simplified and neatly accomplished by using QR decomposition. In addition, the proposed scheme supports parallel matches of all signal sources from a beamforming codebook to improve the processing throughput. The algorithm complexity analysis shows that the proposed scheme outperforms other well-known estimation algorithms significantly under various system configurations. The performance simulation results further reveal that, subject to a beamforming codebook with a 5° angular resolution, the Root Mean Square (RMS) error of angle estimations is only 0.76° when Signal to Noise Ratio (SNR) = 20 dB. The estimation accuracy outpaces other matching pursuit based approaches and is close to that of the classic Estimation of Signal Parameters Via Rotational Invariance Techniques (ESPRIT) scheme but requires only one fifth of its computing complexity. In developing the hardware accelerator design, pipelined Coordinate Rotation Digital Computer (CORDIC) processors consisting of simple adders and shifters are employed to implement the basic trigonometric operations needed in QR decomposition. A systolic array architecture is developed as the computing kernel for QR decomposition. Other computing modules are also realized using various linear systolic arrays and chained together seamlessly to maximize the computing throughput. A Taiwan Semiconductor Manufacturing Company (TSMC) 40 nm CMOS process was chosen as the implementation technology. The gate count of the chip design is 454.4k, featuring a core size of 0.76 mm 2 , and can operate up to 333 MHz. This suggests that one DoA estimation, with up to three signal sources, can be performed every 2.38 μs.

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“…The Bartlett DOA estimator in [12] is shown to be an efficient implementation in terms of computation time. FPGA real-time implementation based on QR and LU decompositions have been reported in [16] and [17], respectively. These methods [16], [17] have been shown to be superior in performance (in terms of estimation accuracy, processing time, and resources utilization) to those of MUSIC and ESPRIT-based algorithms reported in the literature.…”

Section: Introductionmentioning

confidence: 99%

FPGA-Based Hardware Implementation of Computationally Efficient Multi-Source DOA Estimation Algorithms

Hussain¹,

Tayem²,

Soliman³

et al. 2019

IEEE Access

Self Cite

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Hardware implementation of the proposed direction of arrival (DOA) estimation algorithms based on Cholesky and LDL decomposition is presented in this paper. The proposed algorithms are implemented for execution on a field programmable gate array (FPGA) as well as a PC (running LabVIEW) for the multiple non-coherent sources located in the far-field region of a uniform linear array (ULA). Prototype testbeds built using the national instruments (NI) universal software radio peripheral (USRP) software defined radio (SDR) platform and Xilinx Virtex-5 FPGA are originally constructed for the experimental validation of the proposed algorithms. The results from LabVIEW simulations and real-time hardware experiments demonstrate the effectiveness of the proposed algorithms. Specifically, the implementation of the proposed algorithms on a Xilinx Virtex-5 FPGA using the LabVIEW software clarifies their efficiency in terms of computation time and resource utilization, which make them suitable for the real-time practical applications. Moreover, the performance comparison with the QR decomposition-based DOA algorithms as well as similar FPGA-based implementations reported in the literature is conducted in terms of the estimation accuracy, computation speed, and FPGA resources consumed.

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FPGA Hardware Implementation of DOA Estimation Algorithm Employing LU Decomposition

Cited by 26 publications

References 19 publications

Towards Low Latency and Resource-Efficient FPGA Implementations of the MUSIC Algorithm for Direction of Arrival Estimation

Towards Low Latency and Resource-Efficient FPGA Implementations of the MUSIC Algorithm for Direction of Arrival Estimation

A Low Complexity, High Throughput DoA Estimation Chip Design for Adaptive Beamforming

FPGA-Based Hardware Implementation of Computationally Efficient Multi-Source DOA Estimation Algorithms

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