FPGA-Based Hardware Implementation of Computationally Efficient Multi-Source DOA Estimation Algorithms

Hussain, Ahmed; Tayem, Nizar; Soliman, Abdel-Hamid; Radaydeh, Redha M.

doi:10.1109/access.2019.2926335

Cited by 22 publications

(23 citation statements)

References 21 publications

(24 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It requires 3.95µ sec at 40 MHz for DoA estimation that enables to process 0.254 MPPS. Another efficient FPGA-based hardware implementation for DoA estimation using MUSIC algorithm is detailed in [30]. The paper proposes two approaches for DoA estimation using Cholesky and LDL decomposition techniques to avoid the high computational cost of EVD.…”

Section: Related Workmentioning

confidence: 99%

Towards Low Latency and Resource-Efficient FPGA Implementations of the MUSIC Algorithm for Direction of Arrival Estimation

Butt

Khan

Ullah

et al. 2021

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

The estimation of the Direction of Arrival (DoA) is one of the most critical parameters for target recognition, identification and classification. MUltiple SIgnal Classification (MUSIC) is a powerful technique for DoA estimation. The algorithm requires complex mathematical operations like the computation of the covariance matrix for the input signals, eigenvalue decomposition and signal peak search. All these signal processing operations make real-time and resource-efficient implementation of the MUSIC algorithm on Field Programmable Gate Arrays (FPGAs) a challenge.In this paper, a novel design approach is proposed for the FPGAimplementation of the MUSIC algorithm. This approach enables a significant reduction in both FPGA resources and latency. In more detail, the proposed design enables the estimation of DoA in real-time scenarios in 2µsec with 30% to 50% fewer resources as compared to existing techniques.

show abstract

Section: Related Workmentioning

confidence: 99%

Towards Low Latency and Resource-Efficient FPGA Implementations of the MUSIC Algorithm for Direction of Arrival Estimation

Butt

Khan

Ullah

et al. 2021

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

show abstract

“…Regarding the hardware design efficiency of the proposed work, our literature survey cannot identify any other work with chip design. However, there have been works [28][29][30][31] with hardware implementations reported in recent years and all of them are using the FPGA technology. In industry practices, FPGA is usually employed in the cases of system prototyping or when product volume is not large enough to economically justify the Application Specific Integrated Circuit (ASIC) implementation.…”

Section: Comparison With Other Doa Hardware Implementation Workmentioning

confidence: 99%

“…As for the input word length, which may affect the width of data path design, most designs adopt word length between 16 and 21 bits. The reported clock rates vary from 52.5 MHz (design [31]) to 333 MHz (the proposed work). FPGA, because of its programmable feature and a lot of logic overhead, can barely meet the speed achieved by ASIC.…”

Section: Comparison With Other Doa Hardware Implementation Workmentioning

confidence: 99%

See 1 more Smart Citation

A Low Complexity, High Throughput DoA Estimation Chip Design for Adaptive Beamforming

Chen

Ma²,

Hwang

et al. 2020

Electronics

View full text Add to dashboard Cite

Direction of Arrival (DoA) estimation is essential to adaptive beamforming widely used in many radar and wireless communication systems. Although many estimation algorithms have been investigated, most of them focus on the performance enhancement aspect but overlook the computing complexity or the hardware implementation issues. In this paper, a low-complexity yet effective DoA estimation algorithm and the corresponding hardware accelerator chip design are presented. The proposed algorithm features a combination of signal sub-space projection and parallel matching pursuit techniques, i.e., applying signal projection first before performing matching pursuit from a codebook. This measure helps minimize the interference from noise sub-space and makes the matching process free of extra orthogonalization computations. The computing complexity can thus be reduced significantly. In addition, estimations of all signal sources can be performed in parallel without going through a successive update process. To facilitate an efficient hardware implementation, the computing scheme of the estimation algorithm is also optimized. The most critical part of the algorithm, i.e., calculating the projection matrix, is largely simplified and neatly accomplished by using QR decomposition. In addition, the proposed scheme supports parallel matches of all signal sources from a beamforming codebook to improve the processing throughput. The algorithm complexity analysis shows that the proposed scheme outperforms other well-known estimation algorithms significantly under various system configurations. The performance simulation results further reveal that, subject to a beamforming codebook with a 5° angular resolution, the Root Mean Square (RMS) error of angle estimations is only 0.76° when Signal to Noise Ratio (SNR) = 20 dB. The estimation accuracy outpaces other matching pursuit based approaches and is close to that of the classic Estimation of Signal Parameters Via Rotational Invariance Techniques (ESPRIT) scheme but requires only one fifth of its computing complexity. In developing the hardware accelerator design, pipelined Coordinate Rotation Digital Computer (CORDIC) processors consisting of simple adders and shifters are employed to implement the basic trigonometric operations needed in QR decomposition. A systolic array architecture is developed as the computing kernel for QR decomposition. Other computing modules are also realized using various linear systolic arrays and chained together seamlessly to maximize the computing throughput. A Taiwan Semiconductor Manufacturing Company (TSMC) 40 nm CMOS process was chosen as the implementation technology. The gate count of the chip design is 454.4k, featuring a core size of 0.76 mm 2 , and can operate up to 333 MHz. This suggests that one DoA estimation, with up to three signal sources, can be performed every 2.38 μs.

show abstract

“…The welldesigned weights and thresholds of the neural network can be therefore arrived at. And we can embed this algorithm into integrated devices to measure velocity excellently in real time [24], [25]. Finally, the effectiveness of the proposed method will be experimentally verified by measuring the detecting errors of the velocity under the temperature rise condition.…”

Section: Introductionmentioning

confidence: 96%

Extending Velocity Sensor Bandwidth by Compensating Temperature Dependency Based on BP Neural Network

et al. 2019

View full text Add to dashboard Cite

A compensation method for a magnetoelectric velocity sensor (MVS) is always necessary, which can lower the resonance frequency of the measuring system and subsequently extend the measuring bandwidth. In this paper, a novel compensation method is proposed based on the BP neural network under the TensorFlow architecture. Comparing with the existing methods, the new method does not depend upon an accurate model of the MVS any more, whose parameters are badly influenced by the temperature. The dynamic compensator is connected with the sensor. The BP neural network algorithm is used to identify compensation parameters. The dynamic compensator works at state of the optimum parameter all the time to compensate the dynamic performance of MVS by training the weights and thresholds of the neural network. The experiment results show that velocity measurement deviation is within ±5% error band by the dynamic compensator, which can reduce the measurement deviation caused by the variation of temperature and improve the measurement accuracy. The bandwidth can be as low as 0.28Hz. The dynamic compensator is superior to Random Forests and RBF Neutral Network in implement in FPGA/CPLD. Its' accuracy is superior to zero-pole compensation method. This method leads a new way to weaken the temperature variation characteristics of the velocity sensor and improve the measurement performance. INDEX TERMS Velocity sensor, bandwidth expansion, temperature dependence, BP neural network.

show abstract

FPGA-Based Hardware Implementation of Computationally Efficient Multi-Source DOA Estimation Algorithms

Cited by 22 publications

References 21 publications

Towards Low Latency and Resource-Efficient FPGA Implementations of the MUSIC Algorithm for Direction of Arrival Estimation

Towards Low Latency and Resource-Efficient FPGA Implementations of the MUSIC Algorithm for Direction of Arrival Estimation

A Low Complexity, High Throughput DoA Estimation Chip Design for Adaptive Beamforming

Extending Velocity Sensor Bandwidth by Compensating Temperature Dependency Based on BP Neural Network

Contact Info

Product

Resources

About