FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding

Stefo, Riad; Nunez, J.L.; Feregrino, Claudia; Mahapatra, Santanu; Jones, Samuel T.

doi:10.1007/3-540-44687-7_71

Cited by 10 publications

(4 citation statements)

References 5 publications

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“…Although compression can be implemented in this manner, the implementation of the decompressor's search and decode stages in parallel hardware would greatly increase the complexity of the design and it is likely that these aspects would need to be implemented sequentially. Stefo et al [18] described an FPGA implementation of a parallel binary arithmetic coding architecture that is able to process 8 bits per clock cycle compared to the standard 1 bit per cycle.…”

Section: Review Of Parallel Data Compressionmentioning

confidence: 99%

Design and implementation of a lossless parallel high-speed data compression system

Milward

Nunez

Mulvaney

2004

IEEE Trans. Parallel Distrib. Syst.

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Logic density increases have made feasible the implementation of multiprocessor systems able to meet the intensive data processing demands of highly concurrent systems. This paper describes the research and hardware implementation of a highperformance parallel multicompressor chip. A detailed investigation into the performances of alternative input and output routing strategies for realistic data sets demonstrate that the design of parallel compression devices involves important trade offs that affect compression performance, latency, and throughput. The most promising approach is implemented into FPGA hardware and is shown to provide a scalable compression solution at throughputs able to cope with the demands of modern high-bandwidth applications.

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Section: Review Of Parallel Data Compressionmentioning

confidence: 99%

Design and implementation of a lossless parallel high-speed data compression system

Milward

Nunez

Mulvaney

2004

IEEE Trans. Parallel Distrib. Syst.

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“…They are, the modelling phase to keep track of the cumulative frequency information and the coding phase to generate the code with the help of multiple binary coders. Stefo et al (2001) presented in hardware implementation of modelling unit that is able to support parallel binary arithmetic coding. A fully parallel pipelined implementation and execution of both the phases of the multi-alphabet arithmetic encoding algorithm has been tested and synthesised on Xilinx FPGA in Singh (2005, 2007).…”

Section: Literature Survey and Motivationmentioning

confidence: 99%

Efficient Hardware Architecture for Integer Implementation of Multi-Alphabet Arithmetic Coding for Data Mining

Jayavathi

Shenbagavalli

Ram

2017

IJBIDM

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The aim of this paper is to create an efficient hardware architecture for the multi-alphabet arithmetic coding (MA-AC) in semicustom and full custom application specific integrated circuit (ASIC). Generally, hardware realisation of MA-AC involves numerical processing and entropy coding, which employ the floating point (FP) arithmetic which is replaced by integer implementation in such a way that the symbol counts are used instead of probabilities. Novel hardware architecture is designed by modifying the update equations for upper and lower limits of multi-alphabet arithmetic encoder and decoder based on the update equation of the FP implementation. The proposed hardware architectures are synthesised in Xilinx and Altera Field Programmable Gate Array (FPGA) devices to evaluate resource utilisation and speed. Also, the physical design is encountered as ASIC device using Cadence Design environment tsmc 0.18 µm technology which shows area reduction of 12.75% and 23.61% and power consumption of 29.86% and 38.89% for encoder and decoder, respectively.

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“…Firstly, the arithmetic coding stage does not need to be based on a complex multi-alphabet arithmetic coder but a simple and fast binary arithmetic coder would suffice. Secondly, the maintenance of the frequency counts is achieved with a single update operation per node visited [19]. Fig.…”

Section: B Probability Estimatormentioning

confidence: 99%

A Configurable Statistical Lossless Compression Core Based on Variable Order Markov Modeling and Arithmetic Coding

Nunez-Yanez

Chouliaras

2005

IEEE Trans. Comput.

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FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding

Cited by 10 publications

References 5 publications

Design and implementation of a lossless parallel high-speed data compression system

Design and implementation of a lossless parallel high-speed data compression system

Efficient Hardware Architecture for Integer Implementation of Multi-Alphabet Arithmetic Coding for Data Mining

A Configurable Statistical Lossless Compression Core Based on Variable Order Markov Modeling and Arithmetic Coding

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