Design and implementation of a lossless parallel high-speed data compression system

Milward, M.; Nunez, J.L.; Mulvaney, David

doi:10.1109/tpds.2004.7

Cited by 10 publications

(2 citation statements)

References 19 publications

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“…The hardware architecture in [8] can perform massively parallel processing in the variable-length coding stage and in the prediction stage. It achieves lossless pixel throughput by compressing and decompressing blocks during every cycle with 6-12 times the performance improvement compared to the comparative models [13], [26]- [29]. However, from the point of CR, the model [8] still have the room for improvement.…”

Section: Introductionmentioning

confidence: 99%

An Effective Algorithm and Architecture for the High-Throughput Lossless Compression of High-Resolution Images

et al. 2019

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This paper proposes a high-throughput lossless image-compression algorithm based on Golomb-Rice coding and its hardware architecture. The proposed solution increases compression ratios (CRs) while preserving the throughput by taking advantage of a novel parallel variable-length sign coding (PVSC) algorithm that reduces the sign bits to achieve a higher CR. In addition, the proposed solution adopts and modifies the two existing compression algorithms to improve the overall compression performance. The experimental results show that the proposed solution yields an average CR of 3.12, which is higher than those achieved with the previous algorithms. The hardware implementation of the proposed solution for an 8×8 block unit achieves a throughput of 18 GBps and 24 GBps when encoding and decoding, respectively. This hardware performance is enough to handle 7680 × 4320@240-Hz image processing. INDEX TERMSVariable length coding, lossless image compression, DDPCM, Golomb-Rice coding, UHD.

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Section: Introductionmentioning

confidence: 99%

An Effective Algorithm and Architecture for the High-Throughput Lossless Compression of High-Resolution Images

et al. 2019

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“…Due to the simplicity of its implementation, Huffman coding has been used in many hardware data compressors reported in the literature [10]- [12]. However, this technique suffers from two major problems, i.e., it needs an integral number of bits to represent any symbol and performs poorly in adaptive data compression.…”

Section: Introductionmentioning

confidence: 99%

An FPGA-Based Implementation of Multi-Alphabet Arithmetic Coding

Mahapatra

Singh

2007

IEEE Trans. Circuits Syst. I

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A fully parallel implementation of the multi-alphabet arithmetic-coding algorithm, an integral part of many lossless data compression systems, had so far eluded the research community. Although schemes were in existence for performing the encoding operation in parallel, the data dependencies involved in the decoding phase prevented its parallel execution. This paper presents a scheme for the parallel-pipelined implementation of both the phases of the arithmetic-coding algorithm for multisymbol alphabets in high-speed programmable hardware. The compression performance of the proposed scheme has been evaluated and compared with an existing sequential implementation in terms of average compression ratio as well as the estimated execution time for the Canterbury Corpus test set of files. The proposed scheme facilitates hardware realization of both coder and decoder modules by reducing the storage capacity necessary for maintaining the modeling information. The design has been synthesized for Xilinx field-programmable gate arrays and the synthesis results obtained are encouraging, paving the way for further research in this direction.

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An In-Sight Into How Compression Dictionary Architecture Can Affect the Overall Performance in FPGAs

2020

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This paper presents a detailed analysis of various approaches to hardware implemented compression algorithm dictionaries, including our optimized method. To obtain comprehensive and detailed results, we introduced a method for the fair comparison of programmable hardware architectures to show the benefits of our approach from the perspective of logic resources, frequency, and latency. We compared two generally used methods with our optimized method, which was found to be more suitable for maintaining the memory content via (in)valid bits in any mid-density memory structures, which are implemented in programmable hardware such as FPGAs (Field Programmable Gate Array). The benefits of our new method based on a "Distributed Memory" technique are shown on a particular example of compression dictionary but the method is also suitable for another use cases requiring a fast (re-)initialization of the used memory structures before each run of an algorithm with minimum time and logic resources consumption. The performance evaluation of the respective approaches has been made in Xilinx ISE and Xilinx Vivado toolkits for the Virtex-7 FPGA family. However the proposed approach is compatible with 99% of modern FPGAs.

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Design and implementation of a lossless parallel high-speed data compression system

Cited by 10 publications

References 19 publications

An Effective Algorithm and Architecture for the High-Throughput Lossless Compression of High-Resolution Images

An Effective Algorithm and Architecture for the High-Throughput Lossless Compression of High-Resolution Images

An FPGA-Based Implementation of Multi-Alphabet Arithmetic Coding

An In-Sight Into How Compression Dictionary Architecture Can Affect the Overall Performance in FPGAs

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