FPGA Based Low Cost Automatic Test Equipment for Digital Circuits

Bayrakci, Alp Arslan

doi:10.26650/electrica.2018.28093

Cited by 4 publications

(3 citation statements)

References 5 publications

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“…The advances in FPGA technology supports the development of FPGA based low cost ATE. Low cost FPGA based ATE case study can perform functional tests of digital circuits [8].…”

Section: Traditional Methods Of Testingmentioning

confidence: 99%

Design and Implementation of Quad-Site Testing on FPGA Platform

Rabakavi¹,

Siddamal²

2020

Adv. sci. technol. eng. syst. j.

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As manufacturing efficiency has become a main focus of today's business, it is very critical to surge the throughput by developing different test strategies. With throughput, testing cost also has been recognized as the major challenge in the future of leading semiconductors. Reducing test time is a significant effort to maximize throughput as the complexity increases in future generation outcomes and devices. So, low-cost Automatic Test Equipment (ATE) with parallel test can be promoted as the obvious solution for challenges said above. In parallel testing, multiple devices-under-test (DUT) can be tested at a time that enhances way of testing by increasing product flow, limiting gross test times, and efficient usage of tester. The proposed Integrated Circuit (IC) tester is used to implement multi-site testing (Quad-Site testing) and concurrent testing. It exhibits multi-site efficiency which substantially enhances the throughput by reducing test time. Modular, re-configurable test system provides cost-saving solution. To confirm these effects, authors have presented experimental results for Quad site testing of different ICs namely Decoder, Buffer, Multiplexer and Logic gates. This portable IC Tester handles variety of IC packages like Dual Inline Package (DIP), Small Outline Integrated Circuit (SOIC), Thin Shrink Small Outline Package (TSSOP). With functional test, the proposed tester also verified the AC Parametric tests (i) Propagation Delay is 20ns (ii) Operating frequency with 50MHz for Decoder IC (74HC138). The proposed IC tester consumes 70% less power and throughput enhanced by 11% compared to existing IC testers.

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“…The advances in FPGA technology supports the development of FPGA based low cost ATE. Low cost FPGA based ATE case study can perform functional tests of digital circuits [8].…”

Section: Traditional Methods Of Testingmentioning

confidence: 99%

Design and Implementation of Quad-Site Testing on FPGA Platform

Rabakavi¹,

Siddamal²

2020

Adv. sci. technol. eng. syst. j.

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“…Vanitha [14] proposed an FPGA-based automatic test device for detecting behavioral faults in digital components such as flipflops, multiplexers, and full adders. Bayrakci [15] developed a low-cost embedded device and designed software for testing the functionality and transmission delay of MCU chips. Che [16] proposed a memory chip testing system based on FPGA, designing a memory function testing module capable of completing basic read and write operation commands and common memory testing algorithms.…”

Section: Related Workmentioning

confidence: 99%

FATE: A Flexible FPGA-Based Automatic Test Equipment for Digital ICs

Zhang,

Liu,

et al. 2024

Electronics

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The limits of chip technology are constantly being pushed with the continuous development of integrated circuit manufacturing processes and equipment. Currently, chips contain several billion, and even tens of billions, of transistors, making chip testing increasingly challenging. The verification of very large-scale integrated circuits (VLSI) requires testing on specialized automatic test equipment (ATE), but their cost and size significantly limit their applicability. The current FPGA-based ATE is limited in its scalability and support for few test channels and short test vector lengths. As a result, it is only suitable for testing specific chips in small-scale circuits and cannot be used to test VLSI. This paper proposes a low-cost hardware and software solution for testing digital integrated circuits based on design for testability (DFT) on chips, which enables the functional and performance test of the chip. The solution proposed can effectively use the resources within the FPGA to provide additional test channels. Furthermore, the round-robin data transmission mode can also support test vectors of any length and it can satisfy different types of chip test projects through the dynamic configuration of each test channel. The experiment successfully tested a digital signal processor (DSP) chip with 72 scan test pins (theoretically supporting 160 test pins). Compared to our previous work, the work in this paper increases the number of test channels by four times while reducing resource utilization per channel by 37.5%, demonstrating good scalability and versatility.

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“…There have been many researches working on FPGA-based chip testing, but many of them do not use the scan test design due to its complexity, only to simply verify the correctness of functions: For example, Bayrakci proposed an embedded low-cost ATE (ELATE) based on FPGA, which realized the test of function, transmission delay and power consumption [5]; Rabakavi used the FPGA platform to realize the test of simple NAND gate circuit [6]; These works can only verify whether certain operations and functions of the chip are correct, but cannot detect whether the chip has stuck-at faults or transition faults that cause failures.…”

Section: Introductionmentioning

confidence: 99%

PASTE: FPGA-based Portable At-speed Scan Test Equipment

Luo

Yin

et al. 2022

J. Phys.: Conf. Ser.

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The increasing integration and complexity of chips driven by Moore’s Law has placed higher demands on chip verification and testing efforts. Automated Test Equipments (ATE) in conjunction with design for testability can effectively screen out faulty chips, but ATE is too costly and can be functionally redundant to be practical for small and medium-sized chip design companies and scientific research in universities. Therefore, in recent years, there has been a lot of research work on FPGA-based low-cost test equipment, but few studies have used the scan test method and have not been able to realize the at-speed test of the chip. In this paper, we propose a portable, low-cost and configurable FPGA-based chip scan test method, which can realize both normal and at-speed test, and can effectively filter the stuck-at faults and transition faults of the chip. We also optimize the test code size via run-length code compression algorithm and achieve a 68.16% compression rate for the test code, which effectively reduces the overall data storage and transmission overhead.

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FPGA Based Low Cost Automatic Test Equipment for Digital Circuits

Cited by 4 publications

References 5 publications

Design and Implementation of Quad-Site Testing on FPGA Platform

Design and Implementation of Quad-Site Testing on FPGA Platform

FATE: A Flexible FPGA-Based Automatic Test Equipment for Digital ICs

PASTE: FPGA-based Portable At-speed Scan Test Equipment

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