PASTE: FPGA-based Portable At-speed Scan Test Equipment

Abstract

The increasing integration and complexity of chips driven by Moore’s Law has placed higher demands on chip verification and testing efforts. Automated Test Equipments (ATE) in conjunction with design for testability can effectively screen out faulty chips, but ATE is too costly and can be functionally redundant to be practical for small and medium-sized chip design companies and scientific research in universities. Therefore, in recent years, there has been a lot of research work on FPGA-based low-cost test equipment, but few studies have used the scan test method and have not been able to realize the at-speed test of the chip. In this paper, we propose a portable, low-cost and configurable FPGA-based chip scan test method, which can realize both normal and at-speed test, and can effectively filter the stuck-at faults and transition faults of the chip. We also optimize the test code size via run-length code compression algorithm and achieve a 68.16% compression rate for the test code, which effectively reduces the overall data storage and transmission overhead.

FATE: A Flexible FPGA-Based Automatic Test Equipment for Digital ICs

“…Additionally, Carvalho [18] designed automatic test equipment for SAMPA (a gas detection chip), which utilized the chip's DFT to detect internal stuck-at faults. In our previous work [19], we implemented an ATE that uses the scan chain to detect stuck-at faults and delay faults inside the chip. Although these efforts have begun utilizing scan chains to detect structural faults within chips, the need for custom development arises when conducting different fault detections due to the varying test pin configurations of chips, resulting in a lack of versatility.…”

“…The results of the comparison with other works are shown in Table 7. Table 8 shows a detailed comparison with our prior work [19], which includes experimental details. Table 8 indicates that with a 37.5% reduction in resources used per test channel, the number of supported test channels in this work has increased to four times that of the previous work.…”