Design and Implementation of Quad-Site Testing on FPGA Platform

Abstract

As manufacturing efficiency has become a main focus of today's business, it is very critical to surge the throughput by developing different test strategies. With throughput, testing cost also has been recognized as the major challenge in the future of leading semiconductors. Reducing test time is a significant effort to maximize throughput as the complexity increases in future generation outcomes and devices. So, low-cost Automatic Test Equipment (ATE) with parallel test can be promoted as the obvious solution for challenges said above. In parallel testing, multiple devices-under-test (DUT) can be tested at a time that enhances way of testing by increasing product flow, limiting gross test times, and efficient usage of tester. The proposed Integrated Circuit (IC) tester is used to implement multi-site testing (Quad-Site testing) and concurrent testing. It exhibits multi-site efficiency which substantially enhances the throughput by reducing test time. Modular, re-configurable test system provides cost-saving solution. To confirm these effects, authors have presented experimental results for Quad site testing of different ICs namely Decoder, Buffer, Multiplexer and Logic gates. This portable IC Tester handles variety of IC packages like Dual Inline Package (DIP), Small Outline Integrated Circuit (SOIC), Thin Shrink Small Outline Package (TSSOP). With functional test, the proposed tester also verified the AC Parametric tests (i) Propagation Delay is 20ns (ii) Operating frequency with 50MHz for Decoder IC (74HC138). The proposed IC tester consumes 70% less power and throughput enhanced by 11% compared to existing IC testers.