FPGA based Implementation of High Speed Double Precision Floating Point Multiplier with Tiling Technique using Verilog

Abstract

Floating point arithmetic is widely used in many areas, especially scientific computation and signal processing. For many signal processing, and graphics applications, it is acceptable to trade off some accuracy (in the least significant bit positions) for faster and better implementations. However, most of these modern applications need higher frequency or low latency of operations with minimal area occupancy. In this paper we describe an implementation of high speed IEEE 754 double precision floating point multiplier using tiling technique and targeted for Xilinx Virtex-6 Field Programmable Gate Array. Verilog is used to implement the design. The design achieved 436.815 MFlops with latency of seven clock cycles which is 97% fast compared to Xilinx floating point multiplier core. It handles the overflow, underflow cases and truncation rounding mode.

Comparative study of single precision floating point division using different computational algorithms

“…The restoring division is described for sixteen-bit division and well explained its implementation of restoring division algorithm in encryption system [22]. Floating point architectures have low frequency, larger area and high latency in nature described [23]. A reversible Vedic multiplier is designed using reversible logic gates and results in less delay and less power consumption [24].…”

Double Precession Floating Point Multiplier using Schonhage – Strassen Algorithm used for FPGA Accelerator

“…A multiplication operation is the second fundamental operation of the arithmetic unit. However, most of these advanced applications require low latency, high-frequency operations with low area [3], [4], [5]. The FP arithmetic depends on FPGA implementation that defines different arithmetic operations such as addition, subtraction, multiplication, and division.…”