The multiplication strategy is a trending technology in chip programming model; also, it is used in different applications for different purpose. This research aims to develop the floating point double precision Furer Toom cook fast integer multiplication model in the Advanced Encryption Standard process round to enhance the security. In addition, the cryptography algorithms have been broken due to some harmful attack. So the main focus of this present research is to enhance the security measures in communication channel. Moreover, the proposed model is implemented in Xilinx and simulated in cadence 90 nm technology. By comparing the proposed work with recent existing models, the proposed research has reduced the power consumption as 5331.73 nW, thus 89% of power is reduced by the proposed Furer Toom cook multiplication model. The reduction of power enhanced the performance of multiplication algorithm so, while it is utilized in any application, it could not cause any loss of process. In addition, the developed strategy is process within 563 MHz frequency and utilized 11 250 cells. Thus, the proposed model provides better security for all wireless appliances.
The Double Precession Floating Point (DPFP) multiplication algorithm generally use in several applications like arithmetic logic unit, scientific calculators, signal processing and so on. The major limitation of the DPFP arithmetic operation is difficult to calculate 53 x 53 mantissa multiplication, which requires more area. In this research work, a High Speed Schonhage -Strassen Algorithm used for FPGA accelerator (HS-SSA-FPGA) was implemented to provide a low amount of multiplication hardware compared to the conventional methods. The main advantage of the Schonhage Strassen multiplication is that, the multiplication of integer values greater than 5 digits ranging from 2215 to 2217 bit values proves to be efficient. This experimental research work describes SSA architecture and implementation of the FPGA accelerator to get a better output in terms of area and system speed. The FPGA accelerator Control Unit (CU) maximized the Processing Elements (PEs) based on external task request generated from Control Processing Unit (CPU). The SSA-FPGA method was implemented in Xilinx based on Virtex-5 xc5vlx20T by using Verilog HDL Code. The experimental result showed that the proposed method improved the performance of the system in FPGA accelerator compared to the existing methods: Karatsuba and Vedic multiplier. The HS-SSA-FPGA works at 230.14 MHz. The HS-SSA-FPGA multiplication speed is increased by 49 percentages compared with Karatsuba based floating point multiplication..
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