FPGA accelerator for floating-point matrix multiplication

Abstract

Abstract:This study treats architecture and implementation of a FPGA accelerator for double-precision floating-point matrix multiplication. The architecture is oriented towards minimising resource utilisation and maximising clock frequency. It employs the block matrix multiplication algorithm which returns the result blocks to the host processor as soon as they are computed. This avoids output buffering, and simplifies placement and routing on the chip. The authors show that such architecture is especially well suited for full-duplex communication links between the accelerator and the host processor. The architecture requires the result blocks to be accumulated by the host processor; however, the authors show that typically more than 99% of all arithmetic operations are performed by the accelerator. The implementation focuses on efficient use of embedded FPGA resources, in order to allow for a large number of processing elements (PEs). Each PE uses 8 Virtex-6 DSP blocks. Both adders and multipliers are deeply pipelined and use several FPGA-specific techniques to achieve small area size and high clock frequency. Finally, the authors quantify the performance of accelerator implemented in Xilinx Virtex-6 FPGA, with 252 PEs running at 403 MHz (achieving 203.1 GFLOPS), by comparing it to DGEMM function from MKL, ACML, GotoBLAS and ATLAS libraries executing on Intel Core2Quad and AMD Phenom X4 microprocessors running at 2.8 GHz. The accelerator performs 4.5 times faster than the fastest processor/library pair.

High-Level Synthesis Optimization for Blocked Floating-Point Matrix Multiplication

“…Theoretical analysis of an 800 × 800 matrix multiplication shows an execution time of 10 7 cycles. Jovanović and Milutinović [3] present an architecture of = 252 processing elements with local memories to store the input matrices. Large matrices are multiplied by sending blocks to the accelerator.…”

“…The efforts to optimize the I/O result in a significant performance increase to 6,295 MFLOPS for = 124 and = 3 , i.e. 93% of the theoretical performance 0 (124,3) using equation (3).…”

“…As a consequence both input matrices and are sent two times. It is possible to perform a loop interchange and an iteration reordering such that each block matrix is sent only once, a technique also used ad hoc in [3]. By generating the index tuple ( , , ) using the ( , 3)-ary generalized Gray code [5], the -loop becomes outermost and matrices or can be reused in the inner loops.…”

FPGA design and implementation of a matrix multiplier based accelerator for 3D EKF SLAM

“…This is due to the fact that having FPGAs with limited resources it is hardly possible to instantiate that many PEs. A recent work [17] describes an architecture of linear array PEs, similar to those in [16], but achieving an optimal latency of order O(n 2 ) by exploiting full duplex communication with the host processor and at the cost of having it involved during addition of intermediary values.…”

A dynamic optically reconfigurable gate array using a blue laser

“…Recently, field programmable gate arrays (FPGAs) have become widely used as accelerators of software operations [1] [2]. However, since an FPGA is always used along with a single configuration context, its benefits are limited to its programmability.…”