Dataflow has proven to be an attractive computation model for programming digital signal processing (DSP) applications. A restricted version of dataflow, termed synchronous dataflow (SDF), offers strong compile-time predictability properties, but has limited expressive power. In this paper we propose a new type of hierarchy in the SDF domain allowing more expressivity while maintaining its predictability. This new hierarchy semantic is based on interfaces that fix the number of tokens consumed/produced by a hierarchical vertex in a manner that is independent or separate from the specified internal dataflow structure of the encapsulated subsystem. This interface-based hierarchy gives the application designer more flexibility in iterative construction of hierarchical representations, and experimentation with different optimization choices at different levels of the design hierarchy.
Embedded real-time applications in communication systems have significant timing constraints, thus requiring multiple computation units. Manually exploring the potential parallelism of an application deployed on multi-core architectures is greatly time-consuming. This paper presents an open source Eclipse-based framework which aims to facilitate the exploration and development processes in this context. The framework includes a generic graph editor (Graphiti), a graph transformation library (SDF4J) and an automatic mapper/scheduler tool with simulation and code generation capabilities (PREESM). The input of the framework is composed of a scenario description and two graphs, one graph describes an algorithm and the second graph describes an architecture. The rapid prototyping results of a 3GPP Long Term Evolution (LTE) algorithm on a multi-core digital signal processor illustrate both the features and the capabilities of this framework.
Video coding technology has evolved in the past years into a variety of different and complex algorithms. So far the specification of such standard algorithms has been done case by case providing monolithic textual and reference SW specifications, but without any attention on commonalities and the possibility of incremental improvements or modifications of such monolithic standards. The MPEG Reconfigurable Video Coding (RVC) framework is a new ISO standard, currently under development aiming at providing video codec specifications at the level of library functions instead of monolithic algorithms. The possibility to select a subset of standard coding algorithms to specify a decoder that satisfies application specific constraints is very attractive. However, such possibility to reconfigure codecs requires systematic procedures and tools capable of describing the new bitstream syntaxes of such new codecs. Moreover, it is also necessary to generate the associated parsers which are capable to parse the new bitstreams because they are not available "a priori" in the RVC library. This paper further explains the problem and describes the technologies used to describe new bitstream syntaxes within RVC. In addition, the paper describes the methodology and the tools for the validation of bitstream syntaxes descriptions as well as an example of systematic procedures for the direct synthesis of parsers in the same data flow formalism in which the RVC library component are implemented.
Abstract-As the number of cores continues to grow in both digital signal and general purpose processors, tools which perform automatic scheduling from model-based designs are of increasing interest. CAL is a new actor/dataflow oriented language that aims at helping the programmer to express the concurrency and parallelism that are very important aspects of embedded system design as we enter in the multicore era. The design framework is composed by the OpenDF simulation platform, by Cal2C and CAL2HDL code generators and by a multiprocessor scheduling tool called PREESM. Yet in this paper, a subset of CAL is used to describe the application such that the application is SDF. This SDF graph is one starting point of the workflow of PREESM (composed of several plug-ins) to be prototyped/distributed/scheduled over an IP-XACT multiprocessor platform description. The PREESM automatic scheduling consists in statically distributing the tasks that constitute an application between available cores in a multi-core architecture in order to minimize the final latency. This problem has been proven to be NP-complete. An IDCT 2D example will be used as test case of the full framework.
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