2012
DOI: 10.4071/imaps.357
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Formulation of Percolating Thermal Underfills Using Hierarchical Self-Assembly of Microparticles and Nanoparticles by Centrifugal Forces and Capillary Bridging

Abstract: Thermal underfills are crucial to support integration density scaling of future integrated circuit packages. Therefore, a sequential process using hierarchical self-assembly of microparticles and nanoparticles is proposed to achieve percolating thermal underfills with enhanced particle contacts. The three main process steps are assembly of filler particles by centrifugation, formation of nanoparticle necks by capillary bridging, and backfilling of the porous structure with an unfilled capillary adhesive. … Show more

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Cited by 19 publications
(5 citation statements)
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“…∼3 W m −1 K −1 [33] or eutectics that have thermal conductivity values of ∼57 W m −1 K −1 [34]. Eutectic TIMs are comparatively stiff and must be sufficiently thick to prevent failure during thermal expansion and contraction of the adjacent components.…”
Section: Nanostructured Timsmentioning
confidence: 99%
“…∼3 W m −1 K −1 [33] or eutectics that have thermal conductivity values of ∼57 W m −1 K −1 [34]. Eutectic TIMs are comparatively stiff and must be sufficiently thick to prevent failure during thermal expansion and contraction of the adjacent components.…”
Section: Nanostructured Timsmentioning
confidence: 99%
“…As an example, geometries with very thin constrained cavities between silicon layers may be investigated to characterize thermal underfill materials for integrated circuit (IC) chip packaging technologies in application relevant configurations. 9 The shallow 20-60 µm tall cavities and high silicon thermal conductivity lead to overall low thermal resistances of the samples. The cavity thicknesses must be precisely determined in order to minimize the error in the cavity layer thermal conductivity k cavity extraction,…”
Section: Layered Samplesmentioning
confidence: 99%
“…The recently published concept of sequentially created underfills -percolating thermal underfills (PTUF) opens a door to additional design space in this respect [4], [5]. A PTUF layer could have a ratio of filler diameter to cavity height d / h above 0.5 -less than two filler diameters to reach from substrate to chip, or from chip to chip.…”
Section: Introduction: Sub-layering In Underfill Modellingmentioning
confidence: 99%