Fluorine incorporation into HfSiON dielectric for V/sub th/ control and its impact on reliability for poly-Si gate pFET

Inoue, Masashi; Tsujikawa, Shigeo; Mizutani, Masaharu; Nomura, Keigo; Hayashi, Takashi; Shiga, K.; Yugami, J.; Tsuchimoto, J.; Ohno, Y.; Yoneda, Masahiro

doi:10.1109/iedm.2005.1609366

Cited by 33 publications

(22 citation statements)

References 4 publications

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“…It has been reported that fluorination improves the electrical properties and reliability of the dielectric materials, including Al 2 O 3 . [7][8][9][10] The fluorination of Al 2 O 3 for SONOS devices was previously investigated by treating Al 2 O 3 using a low-energy F neutral beam. The results showed that the fluorination of Al 2 O 3 with an F neutral beam can lower the leakage current and significantly improve the memory window characteristics of SONOS devices.…”

Section: Introductionmentioning

confidence: 99%

Fluorination of Aluminum Oxide Gate Dielectrics Using Fluorine Neutral/Ion Beams

Park¹,

Lim²,

Yeon³

et al. 2011

J. Nanosci. Nanotech.

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The effect of the fluorination of aluminum oxide (Al2O3) in an oxide-nitride-aluminum oxide (SiO2-Si3N4-Al2O3, ONA) layer through fluorine (F) ion and neutral-beam treatments on the characteristics of the ONA layer was investigated to study the effect of charge-related damage during F ion beam treatment. The treatment with an F beam at approximately 10 eV energy produced an about-5-nm-thick fluorinated alumina layer by replacing the aluminum-oxygn (Al-O) bonding with Al-F bonding for both the F neutral-beam and F ion beam treatments. Moreover, no significant differences in the physical and chemical properties of the ONA layers treated with the two beams were observed. When the electrical characteristics of the metal-oxide-semiconductor (MOS) devices were compared, however, the lowest leakage current and highest memory window characteristics were observed in the MOS device fabricated with an F neutral beam, due to the Al-F layer formed on the Al2O3 surface. In the case of the MOS device fabricated with the F-ion-beam-treated ONA layer, however, lower electrical characteristics were observed compared to the MOS device fabricated with the F-neutral-beam-treated ONA layer, possibly due to the charge-related damage that occurred during the F ion beam treatment, even though the memory characteristics were improved compared to the reference due to the Al-F layer formed on the Al2O3 surface.

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Section: Introductionmentioning

confidence: 99%

Fluorination of Aluminum Oxide Gate Dielectrics Using Fluorine Neutral/Ion Beams

Park¹,

Lim²,

Yeon³

et al. 2011

J. Nanosci. Nanotech.

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“…A peak electron mobility of 180 cm 2 /V · s was obtained for the YbSi 2−x /HfAlON n-MOSFETs. Further mobility improvement to recently published data [18], [19] may be reachable by using HfSiON and/or forming gas anneal. Fig.…”

Section: Resultsmentioning

confidence: 60%

HfAlON n-MOSFETs incorporating low-work function gate using ytterbium silicide

Wu¹,

Hung²,

Chin³

et al. 2006

IEEE Electron Device Lett.

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Abstract-The authors have fabricated low-temperature fully silicided YbSi 2−x -gated n-MOSFETs that used an HfAlON gate dielectric with a 1.7-nm EOT. After a 600• C rapid thermal annealing, these devices displayed an effective work function of 4.1 eV and a peak electron mobility of 180 cm 2 /V · s. They have additional merit of a process compatible with current very large scale integration fabrication lines.

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“…This should introduce F in the gate stack, which is known to passivate oxide traps and reduce the 1/f noise PSD. [38][39][40][41][42][43][44][45][46] The investigated pMOSFETs had a 0.6 nm chemical (ozone) SiO 2 , formed after standard diluted HF clean, 36 ALD cycles of HfO 2 (∼1.8 nm thickness) and TiN gate followed by a fill metal. 28 As illustrated in Fig.…”

Section: Processing Impactmentioning

confidence: 99%

Low Frequency Noise Analysis of Impact of Metal Gate Processing on the Gate Oxide Stack Quality

Claeys

O’Sullivan

et al. 2018

ECS J. Solid State Sci. Technol.

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A review is given about the impact of the metal gate (MG) in a High-κ/Metal Gate (HKMG) stack on the quality and defectivity of the dielectric, assessed by low-frequency (LF) noise spectroscopy. In a first part, processing aspects are discussed, like, the thickness of the MG and the implementation of a gate-last approach. In the latter case, it is shown that both the cleaning (or dummy gate removal), the growth of the interfacial SiO 2 layer (chemical versus thermal) and a post-HfO 2 -deposition heat or SF 6 plasma treatment need to be optimized for reducing the gate oxide trap density. In a second part, different MGs are compared from a viewpoint of noise magnitude. It is generally found that alternatives to the standard TiN gate yield better static and noise performance. Results will be presented both for scaled planar and FinFET technologies; the latter fabricated on either bulk or Silicon-on-Insulator (SOI) substrates. Also results on Gate-All-Around NanoWire FETs (GAA NWFETs) fabricated on SOI will be included.

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Fluorine incorporation into HfSiON dielectric for V/sub th/ control and its impact on reliability for poly-Si gate pFET

Cited by 33 publications

References 4 publications

Fluorination of Aluminum Oxide Gate Dielectrics Using Fluorine Neutral/Ion Beams

Fluorination of Aluminum Oxide Gate Dielectrics Using Fluorine Neutral/Ion Beams

HfAlON n-MOSFETs incorporating low-work function gate using ytterbium silicide

Low Frequency Noise Analysis of Impact of Metal Gate Processing on the Gate Oxide Stack Quality

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