Floorplanning 1024 cores in a 3D-stacked networkon- chip with thermal-aware redistribution

2011 IEEE 61st Electronic Components and Technology Conference (ECTC)

Lung

Tsai

et al. 2011

Self Cite

Different from traditional static thermal solutions (STS) or dynamic thermal management (DTM), we propose a design of metallic thermal skeletons in order to conduct the heat generated by the virtual core array in this paper. Not only the proposed design can lower the maximum temperature of the hotspot, but improve the thermal uniformity of the test chip. Furthermore, the presented metallic thermal skeletons are composed of the BEOL metallization for connection with the on-chip heat sink. Virtual cores with temperature sensors are also designed to construct a 126-core array and, as the role of the virtual many-core system. The thermal sensor network is based on a ring oscillator whose oscillation frequency is sensitive to temperature. Simulations and theoretical computations have been performed to see the effectiveness of the proposed metallic thermal skeletons. Finally, the infrared radiation thermal images are employed for monitoring the temperature of the virtual cores and that of the metallic thermal skeletons. The experimental results show that the proposed type γ design provides excellent capability for enhancement of thermal conduction and largely enhances the thermal uniformity of the test chip.

Section: B Effective Thermal Conductivity Of the Metallic Thermal Skmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Realization of virtual 126-core system with thermal sensor-network using metallic thermal skeletons

2011 IEEE 61st Electronic Components and Technology Conference (ECTC)

Lung

Tsai

et al. 2011

Self Cite

“…Meanwhile, since the intelligent hand-held devices become popular, the all-in-one processor SOC drives the upgrading mobility in design aspects. The two factors are often regarded as the primary limitations for current processor architectures [1][2] [15]. One solution to overcome the obstacles and continue the performance scaling while still is to integrate on chip many cores and their communication network.…”

Section: Introductionmentioning

confidence: 99%

Hybrid thermal solution for 3D-ICs: Using thermal TSVs with placement algorithm for stress relieving structures

2012 IEEE 62nd Electronic Components and Technology Conference

Tsai

et al. 2012

Self Cite

Stacking die technology using through-silicon-via (TSV) technology has attracted a lot of attention due to various advantages in performance and integration. However, a high temperature environment during the fabrication process of TSV leads to uncontrollable thermal expansion, which then causes a serious reliability problem, the thermal mechanical problem. This problem can result in deformation or mechanical damage to the dies; therefore, it must be resolved. Unlike previous works applying novel components which are not in the standard CMOS process and thus potentially very expensive, this paper proposes to use package process compatible component, micro bumps, to relax the thermal mechanical stress. In addition, we present an efficient algorithm to place micro bumps in appropriate positions to minimize the total number of micro bumps needed. Our simulated results show that significant reduction on the maximum stress can be achieved. Not only the proposed design can lower the maximum temperature of the hotspot, but improve the thermal uniformity of the test chip. Finally, the infrared radiation thermal images are employed for monitoring the temperature of the virtual cores and that of the hybrid thermal solution. The experimental results show that one of proposed design provides excellent capability for enhancement of thermal conduction.

“…Recently, more and more researches investigated the thermal solutions for multi-core systems by using RC-based thermal model [10], [11]. Thermal-aware task allocation methodologies are also popular in literatures [12].…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of 3D-thermal test chip for exploration of package effects

2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)

Lung

Lin

et al. 2011

Self Cite

Thermal solution and thermal management are critical issues in either 2.5D or 3D stacking design, especially when the hotspots are not located next to the heat sink. On the other hand, chip and package designers are eager to know the realtime temperature performance of the stacked chips therefore the workload can be assigned to the proper domain. Hence, a thermal test chip for evaluating the package is proposed in this paper. The thermal sensor network based on a ring oscillator is implemented in this work. Infrared radiation microscopic is employed for inspecting the real-time temperature performance of the chip and package. Four types of package are implemented and experimented by inspection of infrared radiation thermography. The experimental results show that one of proposed design provides good temperature consistency within difference of 0.6 o C with the thermal sensors. Meanwhile, the proposed package has excellent capability for evaluating thermal management of the stacked dies by providing good thermal non-uniformity by 0.035 o C/mm.