Flexfet¿: Independently-Double-Gated SOI Transistor With Variable Vt and 0.5V Operation Achieving Near Ideal Subthreshold Slope

Wilson, Dale G.; Hayhurst, R.; Oblea, Antonio; Parke, S.; Hackler, D.

doi:10.1109/soi.2007.4357895

Cited by 10 publications

(7 citation statements)

References 2 publications

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“…CMOS has moved out of "Classical (geometrically driven) Scaling" where performance was driven by new litho tools leading to smaller transistors that could be easily projected. It is now in the era of "Equivalent Scaling" where performance is driven by changes in technology such as strained silicon [31], high-K/metal gate [32], multi-gate transistors [33] and integration of germanium and compound semiconductors [34]. There is some geometric scaling but this is tapering off and by 2020 will be irrelevant.…”

Section: Equipment Power Consumption Improvements In 2020mentioning

confidence: 99%

GreenTouch GreenMeter Core Network Energy-Efficiency Improvement Measures and Optimization

Elmirghani

Klein

Hinton

et al. 2018

J. Opt. Commun. Netw.

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Section: Equipment Power Consumption Improvements In 2020mentioning

confidence: 99%

GreenTouch GreenMeter Core Network Energy-Efficiency Improvement Measures and Optimization

Elmirghani

Klein

Hinton

et al. 2018

J. Opt. Commun. Netw.

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“…The 'gate' electrode ( Figure(2(a)) is placed above the conducting channel ,is separated from conducting channel by insulating layer. The gate creates an electric field that controls the flow of charge carriers between source and drain through that conducting channel [15]. If the dimensions of IC processes shrinks, unwanted leakage currents grows, particularly between source and drain.…”

Section: Materials and Mathodology 31 Planar Transistormentioning

confidence: 99%

A Methodology for Very Low Power and Small Size Capsule Manufacturing for Wireless Capsule Endoscopy

Rathore¹,

Tiwary²,

Kumar³

2014

IJCA

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We are presenting a method of reducing the size of traditional capsule used in wireless capsule endoscopy (WCE) for. The conventional wireless endoscopic capsule was manufactured on 18µm technology and its size is 26mmx11mm. Here we are using Ultrascale FinFET 16nm technology to reduce the size of capsule. By using this technique the Size of traditional capsule can be reduced by 11-12 % .Using this method leakage current content reduces and power consumption also reduces up to 50% than the traditional one. The device can be operated on a very low operating voltage and thus the life of battery increases. But after the advancement of FPGA technology, here we are emphasizing on ultra-scale technology with 16nm FINFET technology for fabrication of CMOS transistors using 16 nm technology 3D ICs. This method increases system performance and speed upto 2 folds and speed increases upto 30% .

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“…To minimize the SCEs, multigate field effect transistors [3]- [13], such as double-gate transistors [3]- [6], Flexfets [7], and FinFETs or trigate transistors [8], were introduced. Among these structures, the FinFET technology has become a promising candidate to overcome the SCEs due to its superior performance in low-leakage and highdriving currents, compared with other technologies [9]- [11].…”

Section: Introductionmentioning

confidence: 99%

Thermal Modeling of Multi-Fin Field Effect Transistor Structure Using Proper Orthogonal Decomposition

Jia

Helenbrook

Cheng

2014

IEEE Trans. Electron Devices

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An approach is proposed to project thermal behavior in a semiconductor integrated-circuit structure onto a functional space based on the proper orthogonal decomposition (POD). The approach substantially reduces the numerical degrees of freedom (DOF) needed for thermal simulations and requires no assumptions about physical geometry, dimensions, or heat flow paths. The POD approach is applied to a multi-fin FinFET structure having heat sources driven by power pulse excitations with time shifts, width variations, and amplitude modulations. The POD models were compared with detailed numerical simulations (DNS) and it was shown that the POD approach provides thermal solutions that were as accurate and detailed as the DNS. It offers a reduction in numerical DOFs by nearly six orders of magnitude to capture the peak temperatures in multi-fin FinFETs.Index Terms-Compact thermal model (CTM), FinFET, proper orthogonal decomposition (POD), reduced-order model (ROM), thermal simulation.

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Flexfet¿: Independently-Double-Gated SOI Transistor With Variable Vt and 0.5V Operation Achieving Near Ideal Subthreshold Slope

Cited by 10 publications

References 2 publications

GreenTouch GreenMeter Core Network Energy-Efficiency Improvement Measures and Optimization

GreenTouch GreenMeter Core Network Energy-Efficiency Improvement Measures and Optimization

A Methodology for Very Low Power and Small Size Capsule Manufacturing for Wireless Capsule Endoscopy

Thermal Modeling of Multi-Fin Field Effect Transistor Structure Using Proper Orthogonal Decomposition

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