Fixing lithography hotspots on routing without timing discrepancy

Park, Joo Hyun; Paek, Seung Weon; Ha, Naya; Jang, Dae Hyun; Kim, Byung Mu; Won, Hyo Sig; Choi, Kyu Myung

doi:10.1109/socdc.2009.5423858

Cited by 10 publications

(1 citation statement)

References 5 publications

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“…As the result of applying a new method to 32nm chip design, the average rate of fixing hotspots of 1x metal layers on chip design is over 95%, if PHR was applied 2 times at least at almost last ECO stage. Although process hotspot is fixed, we had confirmed that there are no notable timing violations, when result of timing closure was compared [18].…”

Section: Process Hotspot Repairmentioning

confidence: 71%

<title>Yield enhancement with DFM</title>

Paek

Kang

et al. 2012

Design for Manufacturability Through Design-Process Integration VI

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A set of design for manufacturing (DFM) techniques have been developed and applied to 45nm, 32nm and 28nm logic process technologies. A noble technology combined a number of potential confliction of DFM techniques into a comprehensive solution. These techniques work in three phases for design optimization and one phase for silicon diagnostics. In the DFM prevention phase, foundation IP such as standard cells, IO, and memory and P&R tech file are optimized. In the DFM solution phase, which happens during ECO step, auto fixing of process weak patterns and advanced RC extraction are performed. In the DFM polishing phase, post-layout tuning is done to improve manufacturability. DFM analysis enables prioritization of random and systematic failures. The DFM technique presented in this paper has been silicon-proven with three successful tape-outs in Samsung 32nm processes; about 5% improvement in yield was achieved without any notable side effects. Visual inspection of silicon also confirmed the positive effect of the DFM techniques.

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Section: Process Hotspot Repairmentioning

confidence: 71%

<title>Yield enhancement with DFM</title>

Paek

Kang

et al. 2012

Design for Manufacturability Through Design-Process Integration VI

View full text Add to dashboard Cite

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A CMOS Energy Efficient UWB transmitter module

Yuan

Zheng

Yeo

et al. 2009

2009 International SoC Design Conference (ISOCC)

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A low-voltage fully-integrated CMOS power amplifier for mobile WiMAX subscriber station

Pan

Yeo

Anh

et al. 2009

2009 International SoC Design Conference (ISOCC)

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This paper describes a low-voltage fully-integrated CMOS power amplifier for 3.5 GHz mobile WiMAX (IEEE 802.16 standard) subscriber station application based on Chartered's 0.18 ȝm IC process. Through simulations using a supply voltage of 1.8 V indicate a capability to deliver a maximum output power of 24 dBm to a 50 antenna, with P O1dB of 22.7 dBm corresponding to P I1dB of -1.89 dBm. A power gain of 25.87 dB and a voltage gain of 27 dB can be obtained through a 3-stage cascade configuration, and the power added efficiency (PAE) at P O1dB can achieve almost 24%. In addition, this is the first WiMAX power amplifier that can operate under 1.8 V supply in the literature.

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Fixing lithography hotspots on routing without timing discrepancy

Cited by 10 publications

References 5 publications

<title>Yield enhancement with DFM</title>

<title>Yield enhancement with DFM</title>

A CMOS Energy Efficient UWB transmitter module

A low-voltage fully-integrated CMOS power amplifier for mobile WiMAX subscriber station

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