A low-voltage fully-integrated CMOS power amplifier for mobile WiMAX subscriber station

Pan, Ruikun; Yeo, Kiat Seng; Anh, Manh; Boon, Chirn Chye; Gu, Jianlan

doi:10.1109/socdc.2009.5423786

Cited by 1 publication

(2 citation statements)

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“…A "serial AT attachment" (SATA), which is one of the most promising high-speed storage interfaces, is widely used between hosts and external storage devices such as HDDs and disk media, such as a Blu-ray Disc, DVD, and CD, because SATA has a large bandwidth [1][2][3][4][5][6][7][8]. Thus, SATA provides significant improvements in storage performance and features for both desktop and mobile platforms.…”

Section: Introductionmentioning

confidence: 99%

“…In SATA communication using multi-GHz clock signals, reducing large EMI radiation noise and controlling low-jitter high-speed clock signals in various electronic systems are difficult. A spread-spectrum clock generator (SSCG) based on a fractional PLL is the most attractive solutions for these problems in SATA applications [2][3][4][5][6][7][8]. The SSCG must achieve an EMI reduction of more than 7 dB, 250-cycle jitter less than 12 ps, and a variation of less than +/-350ppm in 1.5-GHz output signal frequency in a non-SSC mode [1].…”

Section: Introductionmentioning

confidence: 99%

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A low-jitter 1.5-GHz and large-EMI reduction 10-dBm spread-spectrum clock generator for serial-ATA

Kawamoto

Kokubo

2009

2009 Asia and South Pacific Design Automation Conference

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A low-jitter and large-EMI-reduction spread spectrum clock generator (SSCG) for Serial-ATA (SATA) was developed. A low-jitter voltage-controlled oscillator (VCO) with a high-frequency limiter was developed to prevent the SSCG from malfunctioning. This VCO achieved far less jitter than that of a conventional VCO. An autocalibration technique suitable for this VCO was developed to prevent the SSCG from degrading performance because of process variations. A SATA PHY using a technique for calibrating the SSCG was developed to use an inexpensive but large frequency-variation reference oscillator. This technique was used to calibrate the SSCG output-signal frequency. This is achieved by shifting an SSCG divide ratio by utilizing the difference between an SSCG output signal frequency and a received signal frequency. These techniques were fabricated in 0.13-and 0.15-μm CMOS processes. The proposed SSCG achieved a 10.0-dB reduction in EMI. The variation in the rms jitter at 1.5 GHz with spread-spectrum clocking was reduced from 2.1-7.8 ps to 1.9-3.3 ps by the proposed autocalibration technique. The proposed SATA PHY achieved less than 400-ppm production-frequency tolerance of reference clocks.

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