First foundry platform of complementary tunnel-FETs in CMOS baseline technology for ultralow-power IoT applications: Manufacturability, variability and technology roadmap

Huang, Qianqian; Jia, Rundong; Chen, Cheng; Zhu, Hao; Guo, Lingyi; Wang, Junyao; Wang, Jiaxin; Wu, Chunlei; Wang, Runsheng; Bu, Weihai; Kang, Jing; Wang, Wenbo; Wu, Hanming; Lee, Shiuh-Wuu; Wang, Yangyuan; Huang, Ru

doi:10.1109/iedm.2015.7409756

Cited by 29 publications

(14 citation statements)

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“…Among the possible technological platforms, silicon/silicon-germanium TFETs have the advantage of easy integration with mainstream CMOS [25] [26] [29] [30]. However, the achieved performance is not very rewarding, especially for n-type TFETs, due to fundamental limit set by the indirect band-gap.…”

Section: [2][3][4]mentioning

confidence: 99%

“…This has not been observed in early experimental reports about TFETs mainly because the conduction at very low current levels was often dominated by Trap-Assisted-Tunneling (TAT) and Shockley-Read-Hall (SRH) recombination processes [25]. Nevertheless, the fabrication process for TFETs is also getting more and more controlled and encouraging variability analysis are being reported both for statistically meaningful experimental samples [26], and for simulation based studies [27] [28].…”

Section: Introductionmentioning

confidence: 99%

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Digital and analog TFET circuits: Design and benchmark

Strangio

Settino

Palestri

et al. 2018

Solid-State Electronics

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In this work, we investigate by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs). The analysis reviews and complements our previous papers on these topics. By considering the same devices for all the analysis, we are able to draw consistent conclusions for a wide variety of circuits. A virtual complementary TFET technology consisting of III-V heterojunction nanowires is considered. Technology Computer Aided Design (TCAD) models are calibrated against the results of advanced full-quantum simulation tools and then used to generate look-up-tables suited for circuit simulations. The virtual complementary TFET technology is benchmarked against predictive technology models (PTM) of complementary silicon FinFETs for the 10 nm node over a wide range of supply voltages (VDD) in the sub-threshold voltage domain considering the same footprint between the vertical TFETs and the lateral finFETs and the same static power. In spite of the asymmetry between p-and n-type transistors, the results show clear advantages of TFET technology over FinFET for VDD lower than 0.4V. Moreover, we highlight how differences in the I-V characteristics of FinFETs and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions.

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Section: [2][3][4]mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Digital and analog TFET circuits: Design and benchmark

Strangio

Settino

Palestri

et al. 2018

Solid-State Electronics

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show abstract

“…Also, the transit frequency which decides the speed of the device is inversely proportional to channel length and hence, analogue circuits require larger bandwidth. Moreover, the process variations [5] below 90 nm disturb bias points and hence, affects the linearity of the circuit and degrades resolution. Even though, a lot of MOS improvement techniques such as Junctionless MOS on SOI and other structural modifications has been proposed [7][8][9] but still it is insufficient to withstand the power constraints in resource limited applications.…”

Section: Introductionmentioning

confidence: 99%

Implementation of ∑Δ ADC using electrically doped III‐V ternary alloy semiconductor nano‐wire TFET

Rajan

Patel

Sharma

et al. 2020

Micro & Nano Letters

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In this work, a fast and low‐power sigma delta )(∑normalΔ analogue‐to‐digital converter (ADC) has been developed using a hetero‐material electrically‐doped nano‐wire tunnel field effect transistor (HM‐ED‐NW‐TFET) for the first time. The better gate controllability of nano‐wire and immunity against process variations of electrically doped tunnel field effect transistor (TFET) enhances resolution. In this regard, the first step that has been performed is the material engineering using normalAlxnormalGa1−xnormalSb/normalGaAs1−yPy, to achieve significant driving current at low subthreshold swing and high InormalON/InormalOFF ratio. Secondly, the mole fraction is optimised to upgrade the critical analogue component – the op‐amp. Also, drain under lapping is included in p‐TFET to bring its characteristics as close to n‐TFET. Latter, the look‐up tables of the proposed device has been generated which is used to develop individual block of ∑normalΔ ADC in Cadence. The blocks are well verified and integrated into final ∑normalΔ ADC and its performance is evaluated. Hence, this work has explored the inherent merits of HM‐ED‐NW‐TFET in the development of low power and fast ∑normalΔ ADC by virtue of a high slew rate op‐amp. Therefore, this work contributes a novel approach to explore the characteristics of emerging devices in mixed signal applications.

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“…Of these, two papers utilized III-V TFETs, [42,43] and the other four utilized Si-TFETs. [29,48,49,58] Si-TFETs show good performance owing to the ease of integration. The guidelines for TFET development are as discussed in the previous section; however, there remain difficulties in satisfying all the guidelines.…”

Section: Device Demonstrationsmentioning

confidence: 99%

Material engineering for silicon tunnel field-effect transistors: isoelectronic trap technology

2017

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The tunnel field-effect transistor (TFET) is one of the candidates replacing conventional metal-oxide-semiconductor field-effect transistors to realize low-power-consumption large-scale integration (LSI). The most significant issue in the practical application of TFETs concerns their low tunneling current. Si is an indirect-gap material having a low band-to-band tunneling probability and is not favored for the channel. However, a new technology to enhance tunneling current in Si-TFETs utilizing the isoelectronic trap (IET) technology was recently proposed. IET technology provides a new approach to realize low-power-consumption LSIs with TFETs. The present paper reviews the state-of-the-art research and future prospects of Si-TFETs with IET technology.

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First foundry platform of complementary tunnel-FETs in CMOS baseline technology for ultralow-power IoT applications: Manufacturability, variability and technology roadmap

Cited by 29 publications

References 1 publication

Digital and analog TFET circuits: Design and benchmark

Digital and analog TFET circuits: Design and benchmark

Implementation of ∑Δ ADC using electrically doped III‐V ternary alloy semiconductor nano‐wire TFET

Material engineering for silicon tunnel field-effect transistors: isoelectronic trap technology

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