First- and second-level packaging for the IBM eServer z900

Harrer, H.; Pross, H.; Winkel, T.-M.; Becker, W.D.; Stoller, H.; Yamamoto, Mikio; Abe, S.; Chamberlin, B.J.; Katopis, G.A.

doi:10.1147/rd.464.0397

Cited by 15 publications

(15 citation statements)

References 8 publications

(17 reference statements)

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“…A cursory comparison of the contents of Table I to previous zSeries buses [2], [5] indicates that source synchronous I/O circuit designs have become ubiquitous for the off-MCM interconnects. This trend facilitates the continued increase in data repetition rate, but it provides little or no improvement to the interconnection latency.…”

Section: Z990 Signalingmentioning

confidence: 99%

T-Rex, a blade packaging architecture for mainframe servers

Katopis

Becker

Harrer³

2005

IEEE Trans. Adv. Packag.

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In this paper, we describe the application of the blade packaging concept to the IBM zSeries eServer z990, code-named T-Rex. The advantages of such packaging architecture are highlighted and the challenges for the system performance are identified. The physical and electrical attributes of the five types of buses required to support a processing operating frequency of 1.25 GHz in a symmetric multiprocessing (SMP) architecture with up to 64 processor cores are tabulated. The evolution of the I/O circuits for each of these buses is described along with the bus cycle time and bandwidth trends.Index Terms-Blade servers, computer architecture, computer system design, design methodology, electronic packaging, high-frequency digital signals, mainframe computers, multichip modules (MCMs), semiconductor device packaging.

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Section: Z990 Signalingmentioning

confidence: 99%

T-Rex, a blade packaging architecture for mainframe servers

Katopis

Becker

Harrer³

2005

IEEE Trans. Adv. Packag.

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“…The floorplan shown in Figure 2 illustrates the 16-chip MCM, which consists of eight dualcore processor chips labeled PU0 -PU7 in the figure, four L2 cache chips denoted as SD0 -SD3 1 creating 32 MB of shared second-level cache, a system controller chip (SCC), two memory controller chips (MC0, MC1), and a clock chip (CLK), which provides the clock distribution as well as pervasive function for the MCM. The MCM was designed using the methodology described in [1,5] with upgraded noise-checking tools and routing capability.…”

Section: MCMmentioning

confidence: 99%

“…This three-dimensional packaging structure is one of the factors providing the opportunity to increase the volumetric density of computing power. In a system cage and frame of similar size, the z900 [1], introduced in 2000, had 20 processor cores; the p690, introduced in 2001, had 32 processor cores; and the z990, introduced in 2003, is capable of housing 64 processor cores.…”

Section: Introductionmentioning

confidence: 99%

First- and second-level packaging of the z990 processor cage

Winkel

Becker²,

Harrer

et al. 2004

IBM J. Res. & Dev.

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In this paper, we describe the challenging first-and secondlevel packaging technology of a new system packaging architecture for the IBM eServer z990. The z990 dramatically increases the volumetric processor density over that of the predecessor z900 by implementing a super-blade design comprising four node cards. Each blade is plugged into a common center board, and a blade contains the node with up to sixteen processor cores on the multichip module (MCM), up to 64 GB of memory on two memory cards, and up to twelve self-timed interface (STI) cables plugged into the front of the node. Each glass-ceramic MCM carries 16 chips dissipating a maximum power of 800 W. In this super-blade design, the packaging complexity is increased dramatically over that of the previous zSeries eServer z900 to achieve increased volumetric density, processor performance, and system scalability. This approach permits the system to be scaled from one to four nodes, with full interaction between all nodes using a ring structure for the wiring between the four nodes. The processor frequencies are increased to 1.2 GHz, with a 0.6-GHz nest with synchronous double-data-rate interchip and interblade communication. This data rate over these package connections demands an electrical verification methodology that includes all of the different relevant system components to ensure that the proper signal and power distribution operation is achieved. The signal integrity analysis verifies that crosstalk limits are not exceeded and proper timing relationships are maintained. The power integrity simulations are performed to optimize the hierarchical decoupling in order to maintain the voltage on the power distribution networks within prescribed limits.

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“…In the past few years, as the dimensions of packages and PCBs keep decreasing and the pin counts and routing layers keep increasing, the escape routing problem, which is to route nets from their pins to the component boundaries, becomes more and more critical [3], [10]- [12]. In a PCB bus escape routing instance, the nets of a bus are preferred to be routed together, without mixing with the nets from other buses [4], [5], [7].…”

Section: Introductionmentioning

confidence: 99%

NP-Completeness and an Approximation Algorithm for Rectangle Escape Problem With Application to PCB Routing

Wong

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In this paper, we introduce and study the rectangle escape problem (REP), which is motivated by printed circuit board (PCB) bus escape routing. Given a rectangular region R and a set S of rectangles within R, the REP is to choose a direction for each rectangle to escape to the boundary of R, such that the resultant maximum density over R is minimized. We prove that the REP is NP-complete, and show that it can be formulated as an integer linear programming (ILP). A provably good approximation algorithm for the REP is developed by applying linear programming (LP) relaxation and a special rounding technique to the ILP. In addition, an iterative refinement procedure is proposed as a postprocessing step to further improve the results. Our approximation algorithm is also shown to work for more general versions of REP: weighted REP and simultaneous REP. Our approach is tested on a set of industrial PCB bus escape routing problems. Experimental results show that the optimal solution can be obtained within several seconds for each of the test cases.

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First- and second-level packaging for the IBM eServer z900

Cited by 15 publications

References 8 publications

T-Rex, a blade packaging architecture for mainframe servers

T-Rex, a blade packaging architecture for mainframe servers

First- and second-level packaging of the z990 processor cage

NP-Completeness and an Approximation Algorithm for Rectangle Escape Problem With Application to PCB Routing

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