First- and second-level packaging of the z990 processor cage

Abstract

In this paper, we describe the challenging first-and secondlevel packaging technology of a new system packaging architecture for the IBM eServer z990. The z990 dramatically increases the volumetric processor density over that of the predecessor z900 by implementing a super-blade design comprising four node cards. Each blade is plugged into a common center board, and a blade contains the node with up to sixteen processor cores on the multichip module (MCM), up to 64 GB of memory on two memory cards, and up to twelve self-timed interface (STI) cables plugged into the front of the node. Each glass-ceramic MCM carries 16 chips dissipating a maximum power of 800 W. In this super-blade design, the packaging complexity is increased dramatically over that of the previous zSeries eServer z900 to achieve increased volumetric density, processor performance, and system scalability. This approach permits the system to be scaled from one to four nodes, with full interaction between all nodes using a ring structure for the wiring between the four nodes. The processor frequencies are increased to 1.2 GHz, with a 0.6-GHz nest with synchronous double-data-rate interchip and interblade communication. This data rate over these package connections demands an electrical verification methodology that includes all of the different relevant system components to ensure that the proper signal and power distribution operation is achieved. The signal integrity analysis verifies that crosstalk limits are not exceeded and proper timing relationships are maintained. The power integrity simulations are performed to optimize the hierarchical decoupling in order to maintain the voltage on the power distribution networks within prescribed limits.

Packaging the Blue Gene/L supercomputer

“…This resulted in signals that were always groundreferenced. This design practice, which decreases the return path discontinuities and noise coupling that might result from such discontinuities, has been tried with success in other recent machines [7].…”

Packaging the IBM eServer z990 central electronic complex

“…Individual power boundaries for each PU book require that the power planes within the midplane board be split into four sections for each required voltage level. However, it was necessary to maintain the ground return planes continuously throughout the midplane so that the high-speed signals traveling between PU books would have continuous high-frequency return paths [10]. This segmenting of the power in the midplane concentrated current flow to such an extent that the required midplane current capacity is no greater than that of the z900 eServer.…”

“…Measurements made on a running PU book showed the voltages to be well within the specified range. Reference [10] discusses dc losses from the sense point to the circuits and mid-and high-frequency decoupling.…”

NP-Completeness and an Approximation Algorithm for Rectangle Escape Problem With Application to PCB Routing

“…In the past few years, as the dimensions of packages and PCBs keep decreasing and the pin counts and routing layers keep increasing, the escape routing problem, which is to route nets from their pins to the component boundaries, becomes more and more critical [3], [10]- [12]. In a PCB bus escape routing instance, the nets of a bus are preferred to be routed together, without mixing with the nets from other buses [4], [5], [7].…”