FIR Lowpass filter for signal decimation with 15 MHz clock frequency

Huber, Anton S.; Man, E. De; Schiller, E.; Ulbrich, W.

doi:10.1109/icassp.1986.1168557

Cited by 5 publications

(1 citation statement)

References 2 publications

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“…A decimation filter is designed in [3] for use in delta-sigma coder. It is a FIR low pass filter with 20-bit internal width and clock frequency of 15.36 MHz.…”

Section: Introductionmentioning

confidence: 99%

Serial Adder Based Multiplication and Accumulation Unit (Mac)

Madasamy¹,

Shekhar²

2017

International Journal of Advances in Signal and Image Sciences

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For efficient digital FIR filter applications, the Multiplication and Accumulation (MAC) unit is implemented by using various methods. In a digital filter, the MAC unit is one of the main units for performing multiplications and additions. This paper presents an efficient filter design for digital signal processing (DSP) applications with the reduction of carry propagation. In general, the performance of transpose filter mainly depends on the design of MAC unit. The design of a traditional filter consists of a large number of logical elements and has a high computational delay due to the conventional MAC unit. To design an efficient MAC unit, a serial adder is employed by using 2:1 multiplexer and a shifter block. The proposed work is implemented by using Xilinx ISE synthesis tool.

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“…A decimation filter is designed in [3] for use in delta-sigma coder. It is a FIR low pass filter with 20-bit internal width and clock frequency of 15.36 MHz.…”

Section: Introductionmentioning

confidence: 99%

Serial Adder Based Multiplication and Accumulation Unit (Mac)

Madasamy¹,

Shekhar²

2017

International Journal of Advances in Signal and Image Sciences

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High Throughput Digital Filters

Noll¹

1993

VLSI Implementations for Image Communications

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On the use of modulo arithmetic comb filters in sigma delta modulators

Dijkstra

Nys

Piguet

et al.

ICASSP-88., International Conference on Acoustics, Speech, and Signal Processing

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A novel architecture of one stage Comb decimation filters for Sigma Delta Modulators is described. It performs the decimation of a 1 bit oversampled modulator output to an arbitrary lower output frequency. The use of modulo arithmetic throughout the filter together with the proposed algorithmic decomposition allows a low power and area efficient implementation. This also avoids the storing of the coefficients in a ROM o r the generation of the coefficients with rather complicated up/down counters. The architecture is applicablg to all comb decimation filters with sinc (f) response.A filter with k=3 and a programmable decimation factor has been integrated in a 3 flm CMOS process.

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FIR Lowpass filter for signal decimation with 15 MHz clock frequency

Cited by 5 publications

References 2 publications

Serial Adder Based Multiplication and Accumulation Unit (Mac)

Serial Adder Based Multiplication and Accumulation Unit (Mac)

High Throughput Digital Filters

On the use of modulo arithmetic comb filters in sigma delta modulators

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