Serial Adder Based Multiplication and Accumulation Unit (Mac)

Abstract

For efficient digital FIR filter applications, the Multiplication and Accumulation (MAC) unit is implemented by using various methods. In a digital filter, the MAC unit is one of the main units for performing multiplications and additions. This paper presents an efficient filter design for digital signal processing (DSP) applications with the reduction of carry propagation. In general, the performance of transpose filter mainly depends on the design of MAC unit. The design of a traditional filter consists of a large number of logical elements and has a high computational delay due to the conventional MAC unit. To design an efficient MAC unit, a serial adder is employed by using 2:1 multiplexer and a shifter block. The proposed work is implemented by using Xilinx ISE synthesis tool.

Systolic Fir Filter using Bypass Multiplier

“…MAC unit for efficient filter design is described in [9].This method reduces the carry propagation for serial adder using shifter and 2:1 multiplexer block. systolic array with Linear architecture FIR Residue Number System(RNS) is described in [10].pipelined architecture which is consists of modular cells.…”