On the use of modulo arithmetic comb filters in sigma delta modulators

Abstract

A novel architecture of one stage Comb decimation filters for Sigma Delta Modulators is described. It performs the decimation of a 1 bit oversampled modulator output to an arbitrary lower output frequency. The use of modulo arithmetic throughout the filter together with the proposed algorithmic decomposition allows a low power and area efficient implementation. This also avoids the storing of the coefficients in a ROM o r the generation of the coefficients with rather complicated up/down counters. The architecture is applicablg to all comb decimation filters with sinc (f) response.A filter with k=3 and a programmable decimation factor has been integrated in a 3 flm CMOS process.

A Reconfigurable Delta-Sigma ADC

“…The numerator of (2) represents differentiators whereas the denominator represents integrators. In [5] an approach has been shown, that such filters can be implemented using a cascaded series of three integrators and three differentiators, fig. 3.…”

“…However, the modulators input signal is bipolar with a range from -2.5 V through 2.5 V. Therefore the output values of the sinc filter are settled around zero by adding of K H(jl) (I sin(col ml / 2) \,ml sin(col / 2) ) (1) offset _ 2op length 1 -2 3.1d(Ml)-1 (5) Here M1 is the window size for the arithmetic mean and K the filter order. This can be expressed by a z transfer function.…”

Delta-sigma modulator based mixed-signal BIST architecture for SoC

“…Although they are often used with other digital filter to achieve the desired PCM sampling rate, this application requires only the sinc filters. They are most efficiently implemented by cascading K stages of accumulators operating at the sampling rate of the modu- Figure 6: Frequency Spectrum of a Delta-sigma Modulated Bit-stream lator, followed by K stages of cascaded differentiators operating at the down-sampled rate [19]. The transfer function for a sinc filter with K stages and a down-sample factor M has the general form of…”

A 19-bit low-power multibit sigma-delta ADC based on data weighted averaging

“…The classical architecture of a third-order comb filter consists of a cascade of three accumulators followed by decimation by and by a thirdorder differentiator, as illustrated at Fig. 7(a) [13]. In this design, the last accumulator is reset every cycles so that it directly computes the average of the last values.…”