FIR filters with field-programmable gate arrays

Mintzer, L.

doi:10.1007/bf01607876

Cited by 40 publications

(6 citation statements)

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“…[9] constructs several circuits based on thc digit-serial systolic multiplicr. In [10], [II], [13], [14], [15], [16], the distributcd arithmetic is introduced. Finally, a comparison betwecn…”

Section: Introductionmentioning

confidence: 99%

Design and FPGA implementation of digit-serial fir filters

Dawoud

Masupa

2006

SAIEE Afr. Res. J.

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In this paper the design of a digital-serial N-tap FIR filter with programmable coefficients is presented. The design considers the general case of W-bit sample word and mbit coefficient word. The processing of the data within the filter takes place with full precision. The output data is truncated to W bits. The design introduced the new digit-serial multiplier that guarantees minimum processing time and reduces the hardware requirements. Signamplitude representation for the coefficients and two's complement for the input samples simplified the circuit configuration and allows the use ofa single common two's complement circuit lor all the filter sections. A lOa-tap, 8-bit word length version filter is implemented using an ALTERA FPGA device. The filter can be used in real-time processing with sample rates ranging from 7.5 to 22 MHz

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Section: Introductionmentioning

confidence: 99%

Design and FPGA implementation of digit-serial fir filters

Dawoud

Masupa

2006

SAIEE Afr. Res. J.

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“…[9] Constructs several circuits based on digit-serial systolic multiplier. In [10], [11], [13], [14], [15], [16], the distributed arithmetic is introduced. Finally, a comparison between serial and parallel approaches is presented in [1].…”

Section: Introductionmentioning

confidence: 99%

“…Finally, a comparison between serial and parallel approaches is presented in [1]. From the implementation side, references [2], [3], [4], [7], [8], [9], [10], [11], [12], [13], [14] use Xilinx chips; [15] The organisation of this paper is as follow. In the next section the digit-serial architectures are briefly exposed and the basic digit-serial adder cell is explained.…”

Section: Introductionmentioning

confidence: 99%

A study about FPGA-based digital filters

Valls

Peiro

Sansaloni

et al.

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)

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Esta es la versión de autor de la comunicación de congreso publicada en: This is an author produced version of a paper published in: IEEE Workshop on Signal Processing Systems, SIPS 1998, IEEE, 1998 Abstract -In this paper, a set of operators suitable for digit-serial FIR filtering is presented. The canonical and inverted forms are studied. In each of these structures both the symmetrical and anti-symmetrical particular cases are also covered. All circuits have been implemented using an EPF10K50 Altera FPGA. Main results show that the canonical form presents the less occupation and the higher throughput. The 8-tap filter versions implemented can be applied in real-time processing with sample rate ranging up to 7MHz using the bit-serial versions and up to 25 MHz with the bit-parallel ones.

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“…2.5, the combinational part is implemented by a ROM. For example, when the number of inputs is three, the ROM stores the precomputed values shown in often used to implement convolution operations, since many multipliers and multi-input adders can be replaced by one memory [1,3,6,7,13,14]. This method is applicable only when the coefficients h i are constants.…”

Section: ) Where X (I) Is the Value Of The Input X At The Time I Anmentioning

confidence: 99%

“…To realize FIR filters on FPGAs, we can use Distributed Arithmetic to convert the multiply-accumulation operations into table-lookup operations [7,13,14]. For table lookup, embedded memory blocks in FPGAs can be used.…”

Section: Introductionmentioning

confidence: 99%