Finite-State-Machine Overlay Architectures for Fast FPGA Compilation and Application Portability

Abstract

Despite significant advantages, wider usage of field-programmable gate arrays (FPGAs) has been limited by lengthy compilation and a lack of portability. Virtual-architecture overlays have partially addressed these problems, but previous work focuses mainly on heavily pipelined applications with minimal control requirements. We expand previous work by enabling more flexible control via overlay architectures for finitestate machines. Although not appropriate for control-intensive circuits, the presented architectures reduced compilation times of control changes in a convolution case study from 7 hours to less than 1 second, with no performance overhead and an area overhead of 0.2%. . 2015. Finite-state-machine overlay architectures for fast FPGA compilation and application portability.

A Scalable, Low-Overhead Finite-State Machine Overlay for Rapid FPGA Application Development

“…Several existing approaches have introduced such overlays, but those architectures have limited scalability for large applications and changing control requirements [5]. Similarly, those overlays support only single FSM applications, which can be impractical for parallel applications that experience "state explosion" in their single FSM implementations [4].…”

“…Most existing overlays have focused on applying these tradeoffs on pipelined datapaths with minimal control requirements through the interconnection structure (e.g., [6], [7], [10], [17]). Previous work in control-specialized overlays primarily focused on memory-based FSM implementations [5] using general techniques for FSM synthesis [15] and decomposition techniques from reconfigurable FSM studies (e.g., [3], [8], [9]). The Multi-RAM overlay expands from the 3-RAM overlay [5] with memory decomposition to reduce memory requirements and comparatively requires 15% to 28% fewer lookup tables for individual FSMs, and 77% to 99% fewer lookup tables for more common overlay use cases.…”

“…In this section, we present the new M-RAM architecture, which extends from the 3-RAM architecture [5] with the use of memory decomposition on the state-transition RAM to avoid excessive overhead when an FSM has a wide range in the amount of effective inputs across its states.…”

“…This section describes three FSM overlays from previous works [5], which we extend with the M-RAM overlay.…”

“…The 3-RAM architecture [5] extends from the 2-RAM with transition references. The main source of overhead in the 2-RAM is that the state-transition RAM stores transition data for every combination of inputs, even for the same transition.…”