XBERT: Xilinx Logical-Level Bitstream Embedded RAM Transfusion

Hofmann, Matthew; Tang, Zhiyao; Orgill, Jonathan; Nelson, Jonathan M.; Glanzman, David L.; Nelson, Brent; DeHon, André

doi:10.1109/fccm51124.2021.00009

Cited by 2 publications

(1 citation statement)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, since this is a high-level approach with complex software processing, it is a time-consuming solution (in the range of seconds). Although [21] is another newer interesting example, in this case, only the BRAM content has been targeted.…”

Section: Existing Approachesmentioning

confidence: 99%

A New Methodology to Manage FPGA Distributed Memory Content via Bitstream for Xilinx ZYNQ Devices

et al. 2022

View full text Add to dashboard Cite

This paper proposes a methodology to access data and manage the content of distributed memories in FPGA designs through the configuration bitstream. Thanks to the methods proposed, it is possible to read and write the data content of registers without using the in/out ports of registers in a straightforward fashion. Hence, it offers the possibility of performing several operations, such as, to load, copy or compare the information stored in registers without the necessity of physical interconnections. This work includes two flows that simplify the designing process when using the proposed approach: while the first enables the protection or unprotection of writing on different partial regions through the bitstream, the second permits homogeneous instances of a design implemented in different reconfigurable regions to be obtained without losing efficiency. The approach is based and has been physically validated on the ZYNQ from Xilinx, and when using partially reconfigurable designs, it does not affect the hardware overhead nor the maximum operating frequency of the design.

show abstract

Section: Existing Approachesmentioning

confidence: 99%