Enabling seamless execution on hybrid CPU/FPGA systems: Challenges &amp;amp; directions

Belwal, Meena; Purnaprajna, Madhura; Sudarshan, T. S. B.

doi:10.1109/fpl.2015.7294022

Cited by 11 publications

(5 citation statements)

References 35 publications

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“…The intervention of the operating system (OS) will play a crucial role in such an implementation. The profiler must be designed to communicate with the OS/Job Scheduler [18], [30] and the underlying communication protocols and interrupt mechanisms.…”

Section: A Future Scopementioning

confidence: 99%

“…The profiler extension to heterogeneous platform will further aid its implementation to enable actual dynamic reconfiguration, as pointed to in Section-I. Based on the literature, the components required in an actual dynamically reconfigurable system, namely, 1) Reconfigurable Architectures [30]- [34]-Availability of architectures that can dynamically reconfigure in less time. 2) Software / Operating System (OS) Support [9], [17]- [19], [30], [35]-To enable seamless execution between a processor and reconfigurable architecture in a system, for dynamic resource allocation and swapping configurations between computing elements.…”

Section: ) Dynamic Reconfigurationmentioning

confidence: 99%

“…Based on the literature, the components required in an actual dynamically reconfigurable system, namely, 1) Reconfigurable Architectures [30]- [34]-Availability of architectures that can dynamically reconfigure in less time. 2) Software / Operating System (OS) Support [9], [17]- [19], [30], [35]-To enable seamless execution between a processor and reconfigurable architecture in a system, for dynamic resource allocation and swapping configurations between computing elements. 3) Technology Support [30], [36]- [38] -Enables faster dynamic reconfiguration.…”

Section: ) Dynamic Reconfigurationmentioning

confidence: 99%

“…2) Software / Operating System (OS) Support [9], [17]- [19], [30], [35]-To enable seamless execution between a processor and reconfigurable architecture in a system, for dynamic resource allocation and swapping configurations between computing elements. 3) Technology Support [30], [36]- [38] -Enables faster dynamic reconfiguration. 4) Profiling [11], [15], [20], [21]-To provide support to the Software/OS with both offline and run-time statistics and decide whether to reconfigure dynamically and which specific process.…”

Section: ) Dynamic Reconfigurationmentioning

confidence: 99%

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DynPath–Non-Intrusive Feature-Rich Hardware-Based Execution Path Profiler

Jaswal

Roy

2022

IEEE Access

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Current state of the art application profilers for function/loop (process) based execution paths perform static profiling during design space exploration. Dynamic optimization is a must for heterogenous platforms to achieve low silicon area and better performance in real-time. Hence, it becomes necessary to have a mechanism in the target platform hardware to identify run-time characteristics of various processes of the application code in execution. This should be at both, an individual process level and in the relationship with other co-processes. This paper proposes DynPath -a hardware-based execution path profiler capable of detecting and identifying the processes along with the execution paths, both in a static and dynamic context. It has a rich set of features in comparison to other process-based profilers reported in the literature. Being non-intrusive it does not cause any run-time overheads. To handle the dynamic nature of input data size versus fixed memory row width, the paper proposes a unique approach based on Content Addressable Memory (CAM) for path identification and optimal hardware utilization. Considering that a process can be part of multiple executions paths, the profiler tracks both, the path invocation count, as well as, path-specific process invocation count (PSPIC) for each process. PSPIC logic being computationally intensive, it also proposes an alternative implementation of the PSPIC logic based on resource sharing which helps reduce the total area overhead of the execution path profiler by 87%.

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Section: A Future Scopementioning

confidence: 99%

Section: ) Dynamic Reconfigurationmentioning

confidence: 99%

Section: ) Dynamic Reconfigurationmentioning

confidence: 99%

Section: ) Dynamic Reconfigurationmentioning

confidence: 99%

See 2 more Smart Citations

DynPath–Non-Intrusive Feature-Rich Hardware-Based Execution Path Profiler

Jaswal

Roy

2022

IEEE Access

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“…However, despite the many accelerator success stories, there is a growing need to make FPGA hardware resources in a heterogeneous platform more accessible to application developers who are accustomed to software API abstractions and fast development cycles [61]. The lack of platform abstraction and application portability prevents design reuse and adoption of these platforms for mainstream computing.…”

Section: The Gap Between Fpgas and Asics Is Shrinking With Each New Gmentioning

confidence: 99%

Architecture centric coarse-grained FPGA overlays

Abhishek¹

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Coarse-grained FPGA overlays have emerged as one possible solution to make FPGAs more accessible to application developers who are accustomed to software API abstractions and fast development cycles. Existing overlay architectures offer a number of advantages for general purpose hardware acceleration because of software-like programmability, fast compilation, application portability, and improved design productivity, but at the cost of area and performance overheads due to limited consideration for the underlying FPGA architecture. This thesis explores coarse grained overlays designed using the flexible DSP48E1 primitive on Xilinx FPGAs, allowing pipelined execution of compute kernels at significantly higher throughput. We first evaluate an open source overlay architecture, DySER, mapped on the Xilinx Zynq device and show that DySER suffers from a significant area and performance overhead due to limited consideration for the underlying FPGA architecture. Next, we design and implement a more FPGA targeted overlay architecture that maximizes the peak performance and reduces the interconnect area overhead through the use of an array of DSP block based fully pipelined functional units and an island-style coarse-grained routing network. As the interconnect of the island-style overlay is still excessive, we next explore novel interconnect architectures to further reduce the interconnect area. We next develop DeCO, a cone shaped cluster of FUs, which shows 87% savings in LUT requirements compared to our island-style overlay, for a set of compute kernels. Our experimental evaluation shows that the proposed overlays exhibit frequencies close to the DSP theoretical limit and achieve high performance with significantly reduced area overheads. We also present a methodology for compiling high level language (C/OpenCL) descriptions of compute kernels onto DSP block based coarse-grained overlays. Our mapping flow provides a rapid, vendor independent mapping to the overlay, raising the abstraction level while also reducing compilation time significantly, hence addressing the design productivity issue.

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A Study of Memory Access Patterns as an Indicator of Performance in High-Level Synthesis

Belwal

Sudarshan

2018

Proceedings of First International Conference on Smart System, Innovations and Computing

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Enabling seamless execution on hybrid CPU/FPGA systems: Challenges & directions

Cited by 11 publications

References 35 publications

DynPath–Non-Intrusive Feature-Rich Hardware-Based Execution Path Profiler

DynPath–Non-Intrusive Feature-Rich Hardware-Based Execution Path Profiler

Architecture centric coarse-grained FPGA overlays

A Study of Memory Access Patterns as an Indicator of Performance in High-Level Synthesis

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