Finite Element Analysis and Experiment Validation of Highly Reliable Silicon and Glass Interposers-to-Printed Wiring Board SMT Interconnections

Abstract

Interposers that support high input/output density are becoming critical for system miniaturization and high performance. Silicon and glass are emerging as the primary candidates for such high-density interposers, due to their outstanding dimensional stability, which enables layer-to-layer wiring with small vias. However, silicon and glass have very low coefficient of thermal expansion (CTE), 3-8 ppm/°C, compared with organic printed wiring board (PWB), which has a CTE of 12-18 ppm/°C. The large CTE mismatch between interposer and board raises reliability concern with the ball grid array interconnections. In this paper, compliant dielectric build-up layers laminated on silicon and glass interposers are explored as stress buffers to reduce the strain accumulated in solder interconnections. Finite element method was used to analyze the thermo-mechanical reliability of the interconnections, and predict the fatigue life of solder joints. Three types of low-CTE interposer materials were studied, low-CTE glass (3 ppm/°C), high-CTE glass (8 ppm/°C), and silicon (2.7 ppm/°C). Test vehicles with the above three interposers at a size of 7.2 mm × 7.2 mm with 25-µm-thick polymer stress buffers laminated on both sides were fabricated, and assembled on organic FR-4 boards using Sn96.5Ag3Cu0.5 solder. The reliability of the solder interconnections, with the three different test vehicles, was studied using thermal cycling test from −40°C to 125°C. The high-CTE glass sample was observed to survive 1800 thermal cycles before the first failure was detected in one of the corner joints. Experimental results of fatigue life of interconnections agreed well with finite element modeling results, and reliable interconnections between low-CTE interposer and organic PWB using stress buffers were demonstrated. Based on the validated model, parametric study was conducted to explore the influence of geometry and material properties of interposer on the thermo-mechanical reliability of the solder interconnections, as a guideline for interconnection design of similar interposers.Index Terms-Compliant dielectric, finite element method, model validation, reliability test, thin silicon or glass interposer.

The effect of materials and design on the reliability of through-glass vias for 2.5 D integrated circuits: a numerical study

“…In particular, RXP-4M was chosen in this analysis for its favorable electrical and mechanical properties such as low dielectric loss and low elastic modulus (Sukumaran, 2014). This polymeric material was experimentally shown to be an effective stress buffer layer in integrating glass interposers to printed wire board (PWB) assemblies (Qin et al , 2012, 2014), making it a promising candidate as a buffer layer for TGVs.…”

Effect of Wafer Level Underfill on the Microbump Reliability of Ultrathin-Chip Stacking Type 3D-IC Assembly during Thermal Cycling Tests

“…Given that chip-stacking packages, combined with either silicon-based or glass/ceramic-based interposers, are promising frameworks [ 1 , 2 , 3 , 4 , 5 ] for three-dimensional integrated circuit (3D-IC) integrations [ 6 , 7 , 8 ], microbump (μ-bump) reliability must be enhanced. Processes, such as chip grinding, position adjustment and planarity of assembly, the formation of through-silicon via (TSV), and the composition and dimensions of μ-bumps, should be emphasized to improve the functionality of 3D-IC packages.…”

Time-based reflow soldering optimization by using adaptive Kriging-HDMR method

“…Many other works have been carried out to decrease the warpage of package assemblies during the reflow soldering process. Qin et al (2014) claimed that the warpage increased significantly with an increase in the interposer size in flip-chip packages. Lowering the bonding temperature turned out to be the dominant factor for decreasing the maximum warpage for a problem concerning a chip on glass packaging process with non-conductive adhesives (Chang and Young, 2014).…”