FinFETs: From Devices to Architectures

Bhattacharya, Debajit; Jha, Niraj K.

doi:10.1155/2014/365689

Cited by 156 publications

(41 citation statements)

References 100 publications

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“…In write operation, the maximum voltage that can be reached is called write voltage which is determined by division of voltage between access transistor and pull up transistor. Write stability can be confirmed by strong access transistor driving strength which decreases write voltage [1][2][3].…”

Section: Read and Write Stabilitymentioning

confidence: 96%

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FinFET based 6T SRAM Cell for Nanoscaled Technologies

Dani¹,

Singh²,

Kaur³

2015

IJCA

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FinFET is a non planar modeling device for small size transistors (less than 45nm) will replace traditional planar MOSFETs because of superior ability to control short channel effects, off-state leakage current, power dissipation and propagation delay. Static random access memories (SRAMs) consume nearly 94% of chip area in most present system-onchip (SoC) circuits. In this paper, a standard 6T SRAM cell has been designed using dual gate FinFET transistors and its performance for read/write operation is analyzed in terms of average power consumption, propagation delay, power delay product (PDP) and static noise margin (SNM) for nanoscaled technologies. A comprehensive comparison is carried out with conventional 6T CMOS SRAM cell for 45nm, 32nm and 16nm nanoscaled technologies. A reduction in power delay product by 87.5%, 88.8% and 99.1% in read operation and 90.4%, 89.2% and 96.9% in write operation of FinFET based SRAM cell at 45nm, 32nm and 16nm technology nodes respectively as compared to 6T CMOS SRAM cell. Also an improvement in static noise margin by 27.5%, 31.5% and 8.9% of FinFET based SRAM cell is obtained at 45nm, 32nm and 16nm technology nodes respectively.

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Section: Read and Write Stabilitymentioning

confidence: 96%

“…As the scaling increases scaling of voltage leads to less threshold voltage which will increase speed and also leakage power. To overcome leakage power high threshold voltage can be used but performance degrades by unacceptable margin [1][2][3].…”

Section: Speed and Leakage Currentmentioning

confidence: 99%

FinFET based 6T SRAM Cell for Nanoscaled Technologies

Dani¹,

Singh²,

Kaur³

2015

IJCA

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“…But the difficulty in fabrication of DG MOSFET (Double gate MOSFET) is encountered due to the misalignment of top gate and the back gate [3]. Hence to eliminate the misalignment of gates in DG MOSFET, Finfet [4][5] considered one of the most promising candidates for future generation transistor technologies due to their excellent electrostatic integrity such as Low leakage current, improved short-channel effect and high performance. digital multipliers play significant role in many DSP applications such as fourier transform, filters and in multiplier accumulate unit.…”

Section: Introductionmentioning

confidence: 99%

Comparative Analysis of 4x4 Vedic and Conventional Multiplier with different Adders at 32 nm in different Geometrical Devices

Chopade¹,

Padole²

2017

IJCA

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Devices optimization for power and speed is a major issue in ultra low power applications. The evolution of the MOSFET has proven to be the best choice for next generation processes. Portable device should have good battery life.Processor speed depends mainly on the multiplier. Paper present the analysis of 4-bit multiplier using a Vedic Mathematics (Urdhva Tiryagbhyam sutra) and conventional multiplier with two different adders has been realized using carry look ahead adder and ripple carry adder. Comparative study of multipliers is done for low power requirement and high speed. The main purpose of the paper is to investigate the better adder and multiplication technique. It is observed that the conventional multiplier with Carry look ahead adder is stable and power efficient. Finfet based conventional multiplier with CLA adder is having 10 % less energy delay product than Finfet based VEDIC multiplier with CLA adder and 21.9 % less than FDSOI based conventional multiplier with CLA adder at supply voltage 0.9 V. The variation shows that Finfet based vedic multiplier with CLA adder is having less process variation than fdsoi based conventional multiplier with CLA adder KeywordsRipple Carry Adder; vedic multiplier; Energy Delay Product(EDP)

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“…FinFET has higher carrier mobility, lesser wafer area, faster-switching speed, and higher transconductance in comparison with CMOS technology. 10,11 In FinFET technology, a thin fin of silicon covers the conducting channel. This reduces gate leakage current and short channel effects.…”

mentioning

confidence: 99%

FDSTDL: Low‐power technique for FinFET domino circuits

Garg

Gupta

2019

Circuit Theory & Apps

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Summary Major issues in designing low‐power high‐speed VLSI circuits are propagation delay, power consumption, and noise tolerance. This paper describes fin field‐effect transistor (FinFET) technology for the design of low‐power VLSI circuits. FinFET uses two gates (front and back) in place of a single gate as in complementary metal‐oxide–semiconductor (CMOS) technology for better control of the channel. A new technique foot driven stack transistor domino logic (FDSTDL) is proposed for designing domino logic circuits in order to reduce leakage power and propagation delay. In this paper, 2‐, 4‐, 8‐, and 16‐input domino OR gates are designed and simulated using existing and proposed techniques in CMOS and FinFET technology. Simulation is done on the 32 nm predictive technology model (PTM) node using HSPICE on a direct current (DC) supply voltage of 0.9 V. The proposed circuit is simulated in two modes of FinFET, short gate (SG) mode, and low power (LP) mode. The proposed technique shows maximum power reduction of 43.45% in SG mode in comparison with conditional stacked keeper domino logic (CSK‐DL) technique and maximum delay reduction of 38.66% in LP mode in comparison with coarse‐mesh finite difference (CMFD) technique at a frequency of 200 MHz.

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FinFETs: From Devices to Architectures

Cited by 156 publications

References 100 publications

FinFET based 6T SRAM Cell for Nanoscaled Technologies

FinFET based 6T SRAM Cell for Nanoscaled Technologies

Comparative Analysis of 4x4 Vedic and Conventional Multiplier with different Adders at 32 nm in different Geometrical Devices

FDSTDL: Low‐power technique for FinFET domino circuits

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