Fine grain fault tolerance &amp;#x2014; A key to high reliability for FPGAs in space

Niknahad, Mahtab; Sander, Oliver; Becker, Juergen

doi:10.1109/aero.2012.6187233

Cited by 13 publications

(10 citation statements)

References 22 publications

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“…Further considerations include reduced operating and threshold voltage that, together with higher feature density, will lead to lower SEU immunity. Defect mitigation commands the highest effort in the first instance [31] but a number of approaches nonetheless been reported in recent years as summarised in Table IX. nMR has also been incorporated within FPGA configurations at the block level [65], extended to fine-grained gate redundancy by a method closely related to quadded logic [60] and ultimately appearing at the transistor level via N-modulo redundancy (nMR) [66] and most commonly TMR implementations [67]. A further variation involves scrubbing in which the configuration is periodically refreshed from a golden bitstream [68].…”

Section: A Passive Methodsmentioning

confidence: 99%

“…In [43], multiplexed redundancy was considered at the lowest design levels to improve the reliability of logic gates. Future space exploration will further leverage fine-grained strategies wherever possible, principally because of the additional complexity of incorporating design for active repair [66]. Essentially, once a fault masking strategy has been determined it may be applied fairly readily to hierarchical logic designs, whether fine-grained, cell or block level although evaluation of its resulting impact fault rate behaviour and associated reliability still needs to be performed.…”

Section: A Passive Methodsmentioning

confidence: 99%

See 1 more Smart Citation

Zero-maintenance of electronic systems: Perspectives, challenges, and opportunities

McWilliam

Khan

Farnsworth

et al. 2018

Microelectronics Reliability

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Self-engineering systems that are capable of repairing themselves in-situ without the need for human decision (or intervention) could be used to achieve zero-maintenance. This philosophy is synonymous to the way in which the human body heals and repairs itself up to a point. This article synthesises issues related to an emerging area of self-healing technologies that links software and hardware mitigations strategies. Efforts are concentrated on built-in detection, masking and active mitigation that comprises self-recovery or self-repair capability, and has a focus on system resilience and recovering from fault events. Design techniques are critically reviewed to clarify the role of fault coverage, resource allocation and fault awareness, set in the context of existing and emerging printable/nanoscale manufacturing processes. The analysis presents new opportunities to form a view on the research required for a successful integration of zero-maintenance. Finally, the potential cost benefits and future trends are enumerated.

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Section: A Passive Methodsmentioning

confidence: 99%

Section: A Passive Methodsmentioning

confidence: 99%

Zero-maintenance of electronic systems: Perspectives, challenges, and opportunities

McWilliam

Khan

Farnsworth

et al. 2018

Microelectronics Reliability

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“…This technique is very popular in aerospace applications, where the SEEs have an extended presence and the failure cost is extremely high [5] [6] and it is also used in processor systems hardening approaches [7] [8]. Once the element is tripled the final output is determined by a majority voting.…”

Section: Introduction and Related Workmentioning

confidence: 99%

Fast context reloading lockstep approach for SEUs mitigation in a FPGA soft core processor

Gomez-Cornejo

Zuloaga

Kretzschmar

et al. 2013

IECON 2013 - 39th Annual Conference of the IEEE Industrial Electronics Society

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This paper presents a new approach of the lockstep technique to protect FPGA designs with soft core processors against Single Event Upsets (SEUs) and Single-Event Transients (SETs). One of the biggest drawbacks when using the lockstep technique is the processor context saving and restoring latency. Our approach minimizes the latency thanks to a specific architecture and a specifically adapted 8-bit soft core processor. The proposed architecture is also hardened by using ECC code in memory elements. In this way, this approach combines the benefits of fast SEUs detection with fast restoration of the device functionality. This is demonstrated by running a serial communication application hardened with the new lockstep approach and comparing the results with a Triple Modular Redundancy (TMR) implementation. The design has been implemented in a Xilinx Virtex-5 FPGA.

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“…Although redundancy always comes with the price of extra resource overhead, greater granularity of redundancy is considered more reliable. The most popular technique in aerospace systems is the use of TMR where three identical systems, are operating concurrently and their results are compared by a majority voter [11].…”

Section: Introductionmentioning

confidence: 99%

A Fault-Tolerant Time-Predictable Processor

Gkiokas

Schoeberl

2019

2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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Advancements in commercial space applications have increased interest in deploying FPGA devices with soft processors on satellite systems. Processors are a vital component in all satellite payloads used for control functions and on-board data processing. However, a high integration level within an FPGA causes high sensitivity to ionising radiation-induced errors, requiring mitigation for single event effects to ensure reliable operation. In this paper, a triple-core lock-step processor for radiation-induced soft-errors mitigation is presented that aims to reduce the probability of a processor failure due to softerrors. Aerospace applications are also defined by strict real-time requirements for processors, thus the design is implemented using Patmos, a time-predictable processor of the T-CREST multicore research platform. Index Terms-Fault-tolerance, triple-modular redundancy, lock-step, single event upsets, time-predictable architecture. Core output 1 Core output 2 Core output 3 Core output 1 Core output 2 Core output 3 Voted result Core 1 data valid Core 2 data valid Core 3 data valid Data valid (1) (2) Core output 1 Core output 2 Core output 3 Core output 1 Core output 2 Core output 3 Fault Signal

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Fine grain fault tolerance — A key to high reliability for FPGAs in space

Cited by 13 publications

References 22 publications

Zero-maintenance of electronic systems: Perspectives, challenges, and opportunities

Zero-maintenance of electronic systems: Perspectives, challenges, and opportunities

Fast context reloading lockstep approach for SEUs mitigation in a FPGA soft core processor

A Fault-Tolerant Time-Predictable Processor

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