Fast context reloading lockstep approach for SEUs mitigation in a FPGA soft core processor

Abstract

This paper presents a new approach of the lockstep technique to protect FPGA designs with soft core processors against Single Event Upsets (SEUs) and Single-Event Transients (SETs). One of the biggest drawbacks when using the lockstep technique is the processor context saving and restoring latency. Our approach minimizes the latency thanks to a specific architecture and a specifically adapted 8-bit soft core processor. The proposed architecture is also hardened by using ECC code in memory elements. In this way, this approach combines the benefits of fast SEUs detection with fast restoration of the device functionality. This is demonstrated by running a serial communication application hardened with the new lockstep approach and comparing the results with a Triple Modular Redundancy (TMR) implementation. The design has been implemented in a Xilinx Virtex-5 FPGA.

Lock-V: A heterogeneous fault tolerance architecture based on Arm and RISC-V

“…In a tightly-coupled strategy, the comparison is performed in each system clock, while with a loosely-coupled the comparison can be only done periodically through a checkpoint system [23]. Some processor architectures already provide hardcore lockstep capabilities to assist fault tolerance systems, while other solutions resort FPGA to deploy and customize softcore processors along with extra hardware features to support the lockstep system [16,26,27].…”

A Fault-Tolerant Time-Predictable Processor

“…Another approach is presented in [3], where a DMR architecture is presented. The processors use shared data and program memories but in this design, error correction codes are used after each step of the pipeline, while the outputs are checked with a DMR comperator.…”