A Fault-Tolerant Time-Predictable Processor

Abstract

Advancements in commercial space applications have increased interest in deploying FPGA devices with soft processors on satellite systems. Processors are a vital component in all satellite payloads used for control functions and on-board data processing. However, a high integration level within an FPGA causes high sensitivity to ionising radiation-induced errors, requiring mitigation for single event effects to ensure reliable operation. In this paper, a triple-core lock-step processor for radiation-induced soft-errors mitigation is presented that aims to reduce the probability of a processor failure due to softerrors. Aerospace applications are also defined by strict real-time requirements for processors, thus the design is implemented using Patmos, a time-predictable processor of the T-CREST multicore research platform. Index Terms-Fault-tolerance, triple-modular redundancy, lock-step, single event upsets, time-predictable architecture. Core output 1 Core output 2 Core output 3 Core output 1 Core output 2 Core output 3 Voted result Core 1 data valid Core 2 data valid Core 3 data valid Data valid (1) (2) Core output 1 Core output 2 Core output 3 Core output 1 Core output 2 Core output 3 Fault Signal

On the Security of LEO Satellite Communication Systems: Vulnerabilities, Countermeasures, and Future Trends

“…Digital currency design for debris removal [61] Multi-sensor space debris tracking [62] Reinforcement learning for debris removal [63] Multibistatic radar [64] Space Debris Reconfiguration through remote uplink [56] Periodic reconfigura -tion [57] SEU TMR [58] Fault-tolerant Viterbi decoder [59] Fault-tolerant Turbo decoder [60] Robust constrained inverse BF [52] Jamming Anti-jamming based on IRS [54] DRL and stackelberg game [53] Satellite diversity [55] Coverageexpanding [48] Inter-system interference REM based spectrum sensing [50] Heuristics based RRM [49] SIC [51] Shortest path routing with risk control [44] Node compromise Stochastic blockchain [45] Artificial neural networks based intrusion detection [46] Physical unclonable password [47] Vulnerability intelligent early warning [41] Hijacking Big Data-aided intrusion detection [42] ROAchain based on blockchain [43] Robust BF [38] Wiretap Threshold-based Scheduling [39] IRS [40] Fig. 3: Development timeline of related works for solving security vulnerabilities.…”

“…Monreal et al [57] demonstrated that the periodic reconfiguration of Commercial Off The Shelf (COTS) components have the potential of mitigating the probability of SEUs. Gkiokas et al [58] proposed a fault-tolerant processor for SEU mitigation by employing Triple Module Redundancy (TMR) voting applied to the read/write operation along with memory scrubbing. Gao et al [59], [60] studied the fault tolerance of an SRAM-FPGAbased Viterbi decoder and Turbo decoder.…”