Film thickness constraints for manufacturable strained silicon CMOS

Abstract

This paper studies the effect of the strained silicon thickness on the characteristics of strained silicon MOSFETs on SiGe virtual substrates. NMOSFETs were fabricated on strained silicon substrates with various strained silicon thicknesses, both above and below the strained silicon critical thickness. The low field electron mobility and subthreshold characteristics of the devices were measured. Low field electron mobility is increased by about 1.8 times on all wafers and is not significantly degraded on any of the samples, even for a strained silicon thickness far greater than the critical thickness. From the subthreshold characteristics, however, it is shown that the off-state leakage current is greatly increased for the devices on the wafers with a strained silicon thickness that exceeds the critical thickness. The mechanism of the leakage was examined by using photon emission microscopy. Strong evidence is shown that the leakage mechanism is source/drain electrical shorting caused by enhanced dopant diffusion near misfit dislocations.

EBIC characterization of strained Si/SiGe heterostructures

“…Therefore, a partial strain relaxation could occur during subsequent thermal processing resulting in formation of the misfit dislocations at the strained-Si/SiGe interface. The misfit and threading dislocations in the strained Si layer can essentially affect the device performance [4][5][6]. An additional factor affecting the device performance is the cross-hatching, a large-scale roughness inherent in such structures due to the stress fields associated with the underlying misfit dislocations generated during relaxation in the graded SiGe layer [7].…”

High-Electron-Mobility SiGe on Sapphire Substrate for Fast Chipsets

“…In particular, the collective effect of threading dislocations (TDs) attributed to performance degradation has been observed when other types of crystal defects exist individually [24]. In MOSFET, interface misfit dislocations (MDs) which extend between the source and the drain may become electrically active, resulting in increased off-state leakage [25]. The electrical impact of stacking faults (SFs) on device operation can be seen as a combination of the individual effects of misfit and TDs.…”

Impact of the H2 bake temperature on the structural properties of tensily strained Si layers on SiGe

“…{1 1 1} planes of broken or distorted bond extending through the thickness of the sSi film) or misfit dislocations (MDs) at the interface between sSi and SiGe [7][8][9][24][25][26][27]. It seems likely that SFs would be more deleterious to device operation than MDs [28], although the latter have been shown to act as dopant diffusion pipes in bulk nMOS transistors [29]. At least 10 such images have been acquired for each sample after Secco defect revelation in order to obtain statistically significant values for TDD and LLD.…”