High-Electron-Mobility SiGe on Sapphire Substrate for Fast Chipsets

Kim, Hyun Jung; Park, Yeonjoon; Bae, Hyung Bin; Choi, Sang H.

doi:10.1155/2015/785415

Cited by 11 publications

(8 citation statements)

References 31 publications

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“…Our investigation indicates that preparation of the sapphire substrate surface plays a key role in determining the GaAs film quality. This is in agreement with previous reports that the sapphire wafer treatment before deposition of an epilayer has been effective in reducing twinning . More specifically surfaces with clear step-terraces have generally been effective in encouraging a layer-by-layer growth mode and is widely used to control both the quality and orientation of epilayer in heteroepitaxy. , To explore the role of the sapphire substrate surface on III–V growth, we investigated three different kinds of initial substrate surfaces: (a) a corrugated substrate surface with no step-terrace structure (S1); (b) a weakly defined step-terrace surface (S2); and (c) a well-defined step-terrace surface (S3).…”

Section: Resultsmentioning

confidence: 99%

Crystalline GaAs Thin Film Growth on a c-Plane Sapphire Substrate

Saha

Kumar

Kuchuk

et al. 2019

Crystal Growth & Design

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Crystalline zinc blende GaAs has been grown on a trigonal c-plane sapphire substrate by molecular beam epitaxy. The initial stage of GaAs thin film growth has been investigated extensively in this paper. When grown on c-plane sapphire, it takes (111) crystal orientation with twinning as a major problem. Direct growth of GaAs on sapphire results in three-dimensional GaAs islands, almost 50% twin volume, and a weak in-plane correlation with the substrate. Introducing a thin AlAs nucleation layer results in complete wetting of the substrate, better in-plane correlation with the substrate, and reduced twinning to 16%. Further, we investigated the effect of growth temperature, pregrowth sapphire substrate surface treatment, and in-situ annealing on the quality of the GaAs epilayer. We have been able to reduce the twin volume below 2% and an X-ray diffraction rocking curve line width to 223 arcsec. A good quality GaAs on sapphire can result in the implementation of microwave photonic functionality on a photonic chip.

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Section: Resultsmentioning

confidence: 99%

Crystalline GaAs Thin Film Growth on a c-Plane Sapphire Substrate

Saha

Kumar

Kuchuk

et al. 2019

Crystal Growth & Design

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“…To reinforce that the starting surface must be relatively Sifree in order to maintain low surface roughness, prevent SiC formation, and achieve pristine graphene growth, we attempt to synthesize graphene on Si 0.15 Ge 0.85 (111) sputtered on csapphire using a published procedure. 78 Figure S1a shows a SEM micrograph of the surface after CVD at 960 °C. The surface appears rough and is interspersed with white particles, which presumably are SiC.…”

Section: ■ Results and Discussionmentioning

confidence: 99%

“…■ METHODS Nanoribbon Synthesis. Ge/Si(001) (3 μm) and Si 0.15 Ge 0.85 (111) (fabricated using published procedures 55,78 ) and undoped Ge(001) (purchased from Wafer World, part #1459) substrates were loaded into a horizontal quartz tube furnace in which the furnace can slide over the length of the tube. Prior to nanoribbon synthesis, the CVD chamber was evacuated to <10 −2 Torr using a scroll pump.…”

Section: ■ Results and Discussionmentioning

confidence: 99%

Synthesis of Armchair Graphene Nanoribbons on Germanium-on-Silicon

et al. 2019

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The synthesis of graphene nanoribbons on complementary metal− oxide−semiconductor-compatible substrates is a significant challenge hindering their integration into commercial semiconductor electronics. Here, the bottom-up synthesis of armchair graphene nanoribbons on epilayers of Ge on Si(001) via chemical vapor deposition is demonstrated. The synthesis leverages the previous discovery that graphene crystal growth can be driven with an extreme shape anisotropy on Ge(001) surfaces to directly form nanoribbons. However, compared to nanoribbon synthesis on Ge(001), synthesis on Ge/Si(001) is complicated by the possibility of Si diffusion to the Ge surface and the presence of threading dislocations. Herein, we demonstrate that similar to Ge(001), armchair nanoribbons with faceted edges and sub-10 nm widths can indeed be grown on Ge/Si(001). The nanoribbon synthesis proceeds faster than the diffusion of Si to the Ge surface if a sufficiently thick Ge epilayer is used (e.g., 3 μm), thereby avoiding competing reactions that form SiC. Moreover, threading dislocations in the Ge epilayer are not observed to affect the nucleation or anisotropic growth kinetics of the nanoribbons. These results demonstrate that previous successes in graphene nanoribbon synthesis on Ge(001) can be extended to Si(001) by using epilayers of Ge, motivating the future exploration of this promising platform for hybrid semiconducting graphene/Si electronics.

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“…Saini et al showed that among all other multi-gate architectures, triple gate junctionless devices exhibit superior gate controllability [11-14].Recently, gate-all-around nanowire has become a promising architecture for scaling of MOSFETs [15,16].In this paper, we compare two junctionless multi-gate (JLMG) architectures: junctionless gate-all-around (JL-GAA) and junctionless triple gate (JLTG) each with different high-κ gate oxides to further improve the gate control. These devices derive the advantage of high mobility of Silicon-Germanium material (1538 cm 2 /V • s at 6 × 10 17 cm −3 doping) [17]. Section 2 explains the structure and simulation of these devices.…”

mentioning

confidence: 99%

“…In this paper, we compare two junctionless multi-gate (JLMG) architectures: junctionless gate-all-around (JL-GAA) and junctionless triple gate (JLTG) each with different high-κ gate oxides to further improve the gate control. These devices derive the advantage of high mobility of Silicon-Germanium material (1538 cm 2 /V • s at 6 × 10 17 cm −3 doping) [17]. Section 2 explains the structure and simulation of these devices.…”

mentioning

confidence: 99%

A Comparative Investigation of SiGe Junctionless Triple Gate (JLTG) and Junctionless Gate-All-Around (JL-GAA) MOSFET

Gupta¹,

Varshney²,

Vishwakarma³

et al. 2021

Lecture Notes in Electrical Engineering

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According to the International Technology Roadmap for Semiconductors (ITRS) roadmap [1], the MOSFET sizes shrinking conventionally down to the nanometer regime. We are facing with short channel effects (SCEs) [2, 3] like poor sub-threshold swing, high drain-induced-barrier-lowering (DIBL), increased leakage currents, etc., leading to sub-optimal performance of transistors [4,5]. Researchers have studied several architectures and techniques like junctionless devices [6], multi-gate architecture [7], hetero-high-κ gate oxides [8], lower doping concentrations, high mobility substrate materials that allow lower device size, but without the disadvantage of severe SCEs [9, 10]. Saini et al. showed that among all other multi-gate architectures, triple gate junctionless devices exhibit superior gate controllability [11-14].Recently, gate-all-around nanowire has become a promising architecture for scaling of MOSFETs [15,16].In this paper, we compare two junctionless multi-gate (JLMG) architectures: junctionless gate-all-around (JL-GAA) and junctionless triple gate (JLTG) each with different high-κ gate oxides to further improve the gate control. These devices derive the advantage of high mobility of Silicon-Germanium material (1538 cm 2 /V • s at 6 × 10 17 cm −3 doping) [17]. Section 2 explains the structure and simulation of these devices. Section 3 comprises extensive comparison between the devices basis electrostatic, analog and RF parameters. Conclusions are summarized in Sect. 4.

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High-Electron-Mobility SiGe on Sapphire Substrate for Fast Chipsets

Cited by 11 publications

References 31 publications

Crystalline GaAs Thin Film Growth on a c-Plane Sapphire Substrate

Crystalline GaAs Thin Film Growth on a c-Plane Sapphire Substrate

Synthesis of Armchair Graphene Nanoribbons on Germanium-on-Silicon

A Comparative Investigation of SiGe Junctionless Triple Gate (JLTG) and Junctionless Gate-All-Around (JL-GAA) MOSFET

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