Field-programmable gate array implementation of low-density parity-check codes decoder and hardware testbed

Wetcharungsri, Jutaphet; Buabthong, Narong; Jantarachote, Sakdinan; Sangwongngam, Paramin; Sripimanwat, Keattisak

doi:10.1109/tenconspring.2013.6584426

Cited by 3 publications

(4 citation statements)

References 6 publications

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“…MET-LDPC codes (see [10] [57]) exhibiting low rates combined with the reverse multidimensional reconciliation scheme can achieve excellent correction performance in the CV-QKD system. The signal-to-noise ratio (SNR) of an optical quantum channel is low in such a long distance transmission, thus requiring a low code rate and long code block length.…”

Section: Duhme Et Al Give An Information Reconciliation Methods For C...mentioning

confidence: 99%

“…LDPC code has great application potential and will be widely used in deep space communication, optical fiber communication, satellite digital video (see [6] [7] [8]), digital watermark, magnetic/optical/holographic storage, mobile and fixed wireless communication, cable modulator/demodulator and digital subscriber line (for more details see [9] and [10]).…”

Section: Introductionmentioning

confidence: 99%

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Low-Density Parity-Check Codes: Research Status and Development Direction

Xu¹,

Zheng²,

Tian³

2022

JIS

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In this paper, we conclude five kinds of methods for construction of the regular low-density parity matrix H and three kinds of methods for the construction of irregular low-density parity-check matrix H. Through the analysis of the code rate and parameters of these eight kinds of structures, we find that the construction of low-density parity-check matrix tends to be more flexible and the parameter variability is enhanced. We propose that the current development cost should be lower with the progress of electronic technology and we need research on more practical Low-Density Parity-Check Codes (LDPC). Combined with the application of the quantum distribution key, we urgently need to explore the research direction of relevant theories and technologies of LDPC codes in other fields of quantum information in the future.

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Section: Duhme Et Al Give An Information Reconciliation Methods For C...mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Low-Density Parity-Check Codes: Research Status and Development Direction

Xu¹,

Zheng²,

Tian³

2022

JIS

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“…Due to the limited resources, recent FPGA designs tend to handle this problem by efficient utilization of the embedded RAM capabilities [10,11,12,13,14,15,16]. With this approach, a highly logicconsuming routing network is replaced by simple address management logic blocks.…”

Section: General Architecturementioning

confidence: 99%

“…Although the algorithms and approximation techniques are quite similar, the proposed architectures show much variety in each implementation. ASIC implementations [3,4,5,6,7,8,9] mainly focus on squeezing highly parallelized decoders into smaller silicon areas, whereas FPGA implementations [10,11,12,13,14,15,16,17] focus on efficient utilization of the inherent resources. Therefore, the challenge of optimizing large permutation networks in ASIC designs has mostly turned into designing dynamic RAM-based networks in FPGA designs.…”

Section: Introductionmentioning

confidence: 99%

Dual port ram based layered decoding for Multi Rate Quasi-Cyclic LDPC codes

Yesil

Arslan

2014

2014 12th International Conference on Signal Processing (ICSP)

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This paper presents a generic RAM based FPGA architecture for decoding of Multi Rate Quasi-Cycling LDPC codes. RAM based decoding enables us to reduce permutation networks into simple address controllers. Moreover, utilizing Block RAMs with various aspect ratios in an FPGA provides flexibility ranging from area driven compact designs to fully parallelized high throughput designs. Utilizing the read-first property of the RAMs, the proposed design efficiently exploits the dual port Block RAM resources by accessing all the four ports at the same time. Such facilities of recent FPGA devices have been combined with the well known layered decoding algorithm with non-linearly mapped Min-Sum approximation in order to obtain area efficient yet high throughput decoders. The proposed decoder architecture has been verified on Xilinx XC7Z020 FPGA device for IEEE 802.16e Wimax LDPC codes. 340Mbps of information throughput has been observed at an operating frequency of 150MHz.

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