Fidelity and near-optimality of Elmore-based routing constructions

Boese, Kenneth D.; Kahng, Andrew B.; McCoy, B.A.; Robins, Gabriel

doi:10.1109/iccd.1993.393400

Cited by 72 publications

(52 citation statements)

References 15 publications

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“…To determine the signal delay of an interconnect, we employ the Elmore delay model that has been used in most TD routing work because of its fidelity [7]. A routing tree…”

Section: Delay Model and Objectivementioning

confidence: 99%

Efficient Timing-Driven Incremental Routing for VLSI Circuits Using DFS and Localized Slack-Satisfaction Computations

Dutt

Arslan

2006

Proceedings of the Design Automation &Amp; Test in Europe Conference

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Abstract:In current very deep submicron (VDSM) circuits, incremental routing is crucial to incorporating engineering change orders (ECOs) late in the design cycle. In this paper, we address the important incremental routing objective of satisfying timing constraints in high-speed designs while minimizing wirelength, vias and routing layers. We develop an effective timing-driven (TD) incremental routing algorithm TIDE for ASIC circuits that addresses the dual goals of time-efficiency, and slack satisfaction coupled with effective optimizations. There are three main novelties in our approach: (i) a technique for locally determining slack satisfaction of the entire routing tree when either a new pin is added to the tree or an interconnect in it is re-routed-this technique is used in both the global and detailed routing phases; (ii) an interval-intersection and tree-truncation algorithm, used in global routing, for quickly determining a near-minimumlength slack-satisfying interconnection of a pin to a partial routing tree; (iii) a depth-first-search process, used in detailed routing, that allows new nets to bump and re-route existing nets in a controlled manner in order to obtain better optimized designs. Experimental results show that within the constraint of routing all nets in only two metal layers, TIDE succeeds in routing more than 94% of ECO-generated nets, and also that its failure rate is 7 and 6.7 times less than that of the TD versions of previous incremental routers Standard (Std) and Ripup&Reroute (R&R), respectively. It is also able to route nets with very little (3.4%) slack violations, while the other two methods have appreciable slack violations (16-19%). TIDE is about 2 times slower than the simple TD-Std method, but more than 3 times faster than TD-R&R.

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“…To determine the signal delay of an interconnect, we employ the Elmore delay model that has been used in most TD routing work because of its fidelity [7]. A routing tree…”

Section: Delay Model and Objectivementioning

confidence: 99%

Efficient Timing-Driven Incremental Routing for VLSI Circuits Using DFS and Localized Slack-Satisfaction Computations

Dutt

Arslan

2006

Proceedings of the Design Automation &Amp; Test in Europe Conference

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“…Due to the nonuniformity of the interconnects, each segment is modeled as a distributed RC line with different impedance characteristics. In order to analyze the delay of a line, the distributed Elmore delay model has been adopted due to the simplicity and high fidelity of this model [94]. The accuracy of the model can be further improved as discussed in [95].…”

Section: Pavlidis and Friedman: Interconnect-based Design Methodologiesmentioning

confidence: 99%

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

2009

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“…Based on the Elmore delay model [51], the key concept in the heuristic is that the optimum via placement depends primarily upon the size of the allowed interval (that is estimated or known after an initial placement) rather than the exact location of the via.…”

Section: Fig 7 Interplane Interconnect Connecting Two Circuits Locamentioning

confidence: 99%

Physical Design Issues in 3-D Integrated Technologies

Pavlidis¹,

Friedman

2010

IFIP Advances in Information and Communication Technology

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Abstract. Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achieved in 3-D manufacturing technologies. Advanced design methodologies for 2-D circuits are not sufficient to manage the added complexity caused by the third dimension. Consequently, design methodologies that efficiently handle the added complexity and inherent heterogeneity of 3-D circuits are necessary. These 3-D design methodologies should support robust and reliable 3-D circuits, while considering different forms of vertical integration, such as systems-in-package and 3-D ICs with fine grain vertical interconnections. The techniques described in this chapter address important physical design issues and fundamental interconnect structures in the 3-D design process.

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Fidelity and near-optimality of Elmore-based routing constructions

Cited by 72 publications

References 15 publications

Efficient Timing-Driven Incremental Routing for VLSI Circuits Using DFS and Localized Slack-Satisfaction Computations

Efficient Timing-Driven Incremental Routing for VLSI Circuits Using DFS and Localized Slack-Satisfaction Computations

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

Physical Design Issues in 3-D Integrated Technologies

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