Fermi-Level Pinning at Metal/High-$k$ Interface Influenced by Electron State Density of Metal Gate

Yang, Zhong; Huang, Anping; Zheng, Xiaoyan; Xiao, Zhisong; Liu, X Y; Zhang, X W; Chu, Paul K.; Wang, W W

doi:10.1109/led.2010.2062171

Cited by 11 publications

(7 citation statements)

References 19 publications

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“…This phenomenon is called Fermi-level pinning (FLP) which causes EWF of the nMOS (pMOS) to be much greater (smaller) than the corresponding work function in vacuum [8]. The electron density in the metal gate can also influence the EWF [9]. Stacked metal layers used in the gate structure have been investigated.…”

Section: Interface Dipole Formation In Mos Stackmentioning

confidence: 99%

Interface dipole engineering in metal gate/high-k stacks

et al. 2012

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Although metal gate/high-k stacks are commonly used in metal-oxide-semiconductor field-effect-transistors (MOSFETs) in the 45 nm technology node and beyond, there are still many challenges to be solved. Among the various technologies to tackle these problems, interface dipole engineering (IDE) is an effective method to improve the performance, particularly, modulating the effective work function (EWF) of metal gates. Because of the different electronegativity of the various atoms in the interfacial layer, a dipole layer with an electric filed can be formed altering the band alignment in the MOS stack. This paper reviews the interface dipole formation induced by different elements, recent progresses in metal gate/high-k MOS stacks with IDE on EWF modulation, and mechanism of IDE. high-k dielectrics, metal gate, interface dipole, MOS stack, effective work function Citation:Huang A P, Zheng X H, Xiao Z S, et al. Interface dipole engineering in metal gate/high-k stacks. Chin Sci Bull, 2012, 57: 28722878, doi: 10.1007/s11434-012-5289-6As poly-Si/SiO 2 is replaced by metal gate/high-k stacks in the 45 nm MOS technological node and beyond, the interface becomes more complicated and there are still many challenges to be solved [1,2], such as the flatband voltage shift (V fb shift) [3]. Hence, the properties of the high-k layer must be reconsidered carefully. It has recently been reported that the interface dipole can induce potential difference across the interface and change the band alignment of the MOS stack, and this phenomenon can be exploited to modulate the V fb shift [4][5][6]. Elemental doping can also improve the performance of the high-k layer. Interface dipole engineering (IDE) by varying the dopants or inserting capping layers has attracted much attention in MOS technology. Not only can this technique control the V fb shift, but also the properties of the high-k dielectrics can be improved [7]. This paper reviews the formation of interface dipole, recent research progresses on IDE and effective work function (EWF) modulation, as well as mechanism of IDE in metal gate/high-k MOS stacks. Interface dipole formation in MOS stackTo control the threshold voltage (V th ), work function of a metal gate should be near the conduction band of Si (~4.3 eV) for nMOS and valence band (~5.2 eV) for pMOS. However, only very few metals can satisfy these requirements and furthermore, when a metal is in contact with the high-k layer, its Fermi-level will tend to be at the neutral level of the high-k layer. This phenomenon is called Fermi-level pinning (FLP) which causes EWF of the nMOS (pMOS) to be much greater (smaller) than the corresponding work function in vacuum [8]. The electron density in the metal gate can also influence the EWF [9]. Stacked metal layers used in the gate structure have been investigated. Misra et al. [10] reported that a metal gate stack using Ru-Ta alloys could yield a work function compatible with nMOS. Lin et al. [11] implanted N into a Mo gate that was

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Section: Interface Dipole Formation In Mos Stackmentioning

confidence: 99%

Interface dipole engineering in metal gate/high-k stacks

et al. 2012

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“…The origins are unclear, leading to an effective work function (eWF) for the metal, different from the bulk values. Some reports in the literature attribute this shift to Fermi level pinning (FLP) caused either by metal-induced gap states [13][14][15] or charged defects/oxygen transfers, at the metal/high-k interface [12,16,17]. Dipole formation at the high-k/SiO 2 interface due to oxygen vacancies [18,19], and/or the energy offsets between the high-k and SiO 2 [20], have also been suggested in the literature as possible root causes for an eWF.…”

Section: Work Function Extraction Methodologymentioning

confidence: 99%

Understanding the Origin of Metal Gate Work Function Shift and Its Impact on Erase Performance in 3D NAND Flash Memories

et al. 2021

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We studied the metal gate work function of different metal electrode and high-k dielectric combinations by monitoring the flat band voltage shift with dielectric thicknesses using capacitance–voltage measurements. We investigated the impact of different thermal treatments on the work function and linked any shift in the work function, leading to an effective work function, to the dipole formation at the metal/high-k and/or high-k/SiO2 interface. We corroborated the findings with the erase performance of metal/high-k/ONO/Si (MHONOS) capacitors that are identical to the gate stack in three-dimensional (3D) NAND flash. We demonstrate that though the work function extraction is convoluted by the dipole formation, the erase performance is not significantly affected by it.

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“…The net charge density of the metal-dielectric interface ρ dm (x) is determined by the states between E cnl,d and E fm,eff , while the image charge density of the metal ρ m (x) depends on the states between E fm and E fm,eff . The charge density is determined by the following equations: [11,12]…”

Section: Methodsmentioning

confidence: 99%

“…The pinning factor S can be further calculated by the continuity of the vacuum level and charge neutralization conditions. [11] The calculation provides a more precise value of S than that in MIGS. However, there are still few results concerning the change of the electron state density and interface state density.…”

Section: Introductionmentioning

confidence: 99%

Fermi level pinning effects at gate–dielectric interfaces influenced by interface state densities

Hong¹,

Han²,

Lyu³

et al. 2015

Chinese Phys. B

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The dependences of Fermi-level pinning on interface state densities for the metal–dielectric, ploycrystalline silicon–dielectric, and metal silicide–dielectric interfaces are investigated by calculating their effective work functions and their pinning factors. The Fermi-level pinning factors and effective work functions of the metal–dielectric interface are observed to be more susceptible to the increasing interface state densities, differing significantly from that of the ploycrystalline silicon–dielectric interface and the metal silicide–dielectric interface. The calculation results indicate that metal silicide gates with high-temperature resistance and low resistivity are a more promising choice for the design of gate materials in metal-oxide semiconductor (MOS) technology.

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Fermi-Level Pinning at Metal/High-$k$ Interface Influenced by Electron State Density of Metal Gate

Cited by 11 publications

References 19 publications

Interface dipole engineering in metal gate/high-k stacks

Interface dipole engineering in metal gate/high-k stacks

Understanding the Origin of Metal Gate Work Function Shift and Its Impact on Erase Performance in 3D NAND Flash Memories

Fermi level pinning effects at gate–dielectric interfaces influenced by interface state densities

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