FDTD algorithm to achieve absolute stability in performance analysis of SWCNT interconnects

Venkataiah, C.; Satyaprasad, K.; Prasad, T. Jayachandra

doi:10.1007/s10825-017-1125-1

Cited by 12 publications

(9 citation statements)

References 19 publications

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“…Therefore, researchers are working to design the infrastructure, circuits, processes and interconnections. [44][45][46] To date, CNT thin-film FETs have been intensively…”

Section: Inverter and Ternary Content-addressable Memory Based On Car...mentioning

confidence: 99%

“…Therefore, researchers are working to design the infrastructure, circuits, processes and interconnections. [ 44–46 ] To date, CNT thin‐film FETs have been intensively studied in multiple application areas, including several basic logic and storage devices, [ 47–53 ] synaptic devices, [ 54–57 ] healthcare devices, [ 58,59 ] radio frequency technology, [ 60,61 ] biosensing and detection technology, [ 62–65 ] communication engineering, [ 66,67 ] electrical applications, such as compressor, [ 68 ] ultralow power device, [ 69 ] AC amplifier, [ 70 ] and display electronics, [ 71 ] and so on. In the case of TCAM, as far as we know, the hybrid method of making TCAM has not been tried.…”

Section: Introductionmentioning

confidence: 99%

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Inverter and Ternary Content‐Addressable Memory Based on Carbon Nanotube Transistors Using Chemical Doping Strategy

Yuan

Wang

et al. 2022

Adv Elect Materials

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Carbon nanotubes (CNTs) have attracted much attention in transistors because of their unique structure and electrical properties. However, the implementation of transistor polarity control and complementary logic functions remains a key challenge. In this work, the polarity of carbon nanotube transistors using chemical doping strategy is modulated. By triethyl oxonium hexachloro antimonate doping and polyethylene imine doping with chemically modified, p‐type CNTs and n‐type CNTs as the transistor channel of the bottom gate structure field effect transistors are prepared. An inverter is constructed by connecting p‐type transistor and n‐type transistor in series. The inverter has a voltage hysteresis window and gain over 20.5. A Schmitt trigger with operating frequency over 2 MHz is built based on high‐low conversion of inverter output voltage during dual‐scan has different threshold voltage characteristics. Two inverters are used to construct a ternary content‐addressable memory cell with four transistors, which has an on/off ratio up to 104, a data retention characteristic of 104 s, and a good stability of more than 1000 cycles, indicating the great potential of practical application in future computing‐in memory.

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“…Therefore, researchers are working to design the infrastructure, circuits, processes and interconnections. [44][45][46] To date, CNT thin-film FETs have been intensively…”

Section: Inverter and Ternary Content-addressable Memory Based On Car...mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Inverter and Ternary Content‐Addressable Memory Based on Carbon Nanotube Transistors Using Chemical Doping Strategy

Yuan

Wang

et al. 2022

Adv Elect Materials

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“…Because of the high mobility of electrons movement near ballistic transport and high driving capacity and smaller area, the CNTFETs are become promising alternate for CMOS technology especially when the device scaled at nanometer range. The authors [21][22][23][24][25][26] revealed that CNTFET outperforms compared to CMOS for both circuits and transmission lines. The positive feedback logic shown superior performance in the design of BCAM cells and other circuits needed to realize the BCAM array such as priority encoder, decoder and other logic gates [27,28].…”

Section: Fig1 General 4x4 Bcam Arraymentioning

confidence: 99%

Design and Performance Analysis of Low Power High Speed 4x4 CNTFET Binary Content Addressable Memory Array

Gangadhar*,

Babulu

2019

IJEAT

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In this paper, Carbon Nanotube Field Effect Transistor (CNTFET) based Binary Content Addressable Memory (BCAM) array is presented. The CAM array comprises of address decoders, encoders, data drivers and BCAM cells. Performance analysis is carried for 4X4 BCAM array. Each BCAM cell is designed based on adiabatic logic with optimum CNTFET parameter for low power and high speed applications. The performance of proposed BCAM array is analyzed for average power, peak power and search delay. The proposed CNTFET based BCAM array show improvement in the performance compared to that of complementary metal oxide semiconductor (CMOS) based BCAM array. The average power and peak power of the proposed 4x4 CNTFET BCAM array are in the range of micro watt (µW) while it is in the range of milli watt (mW) for CMOS based BCAM array. The search delay of the proposed 4X4 CNTFET BCAM array is improved by 32.3% compared to that of CMOS based BCAM array. All simulations are conducted for both CNTFET and CMOS based BCAM cells, BCAM array in HSPICE at 32 nm technology.

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“…Hence, increasing the amount of power dissipation integrated circuits. As improvement in technology or scaling will leads to have also provides in a significant may increase in parasitic in interconnects wires [6][7][8][9][10][11][12]. Inductive effect and capacitive coupling effect gives interconnect wire coupling crosstalk significant and cause many signal integrity problems.…”

Section: Introductionmentioning

confidence: 99%

Crosstalk Analysis of On-chip VLSI Interconnects

Jayamma¹,

Ramanjaneyulu²,

Sathish³

et al. 2022

International Journal of Emerging Research in Engineering, Science, and Management

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In this paper dynamic crosstalk is analyzed for coupled on-chip VLSI interconnects in different conditions. The proposed work has taken the MOS transistor analytical expressions. In this work, calculated the transition delays and different timings of the interconnect aggressor and interconnect victim drivers for in-phase switching and out-of-phase switching. All the calculated results are compared with simulations in SPICE. The average error in the transmission delay using SPICE is 2.02 and 3.274% for the interconnect aggressor and interconnect victim buffers for in phase switching, respectively. The average errors in the same are 2.3 and 1.87% for out phase switching event.

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FDTD algorithm to achieve absolute stability in performance analysis of SWCNT interconnects

Cited by 12 publications

References 19 publications

Inverter and Ternary Content‐Addressable Memory Based on Carbon Nanotube Transistors Using Chemical Doping Strategy

Inverter and Ternary Content‐Addressable Memory Based on Carbon Nanotube Transistors Using Chemical Doping Strategy

Design and Performance Analysis of Low Power High Speed 4x4 CNTFET Binary Content Addressable Memory Array

Crosstalk Analysis of On-chip VLSI Interconnects

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