In many digital processors, the power dissipation in apart [2,3]. In this method, the total number of transitions the bus is a major part of the total chip power dissipation. For occurring between the newly arrived data and the present CMOS circuits most power is dissipated as a dynamic power data on the bus is first calculated. If this number is more for charging and discharging node capacitances. In non deep than half the number of sub-micron technology, these capacitances are mainly the substrate capacitances of the bus wires where as in deep submicron technology inter wire capacitance also contribute to total capacitance. The main objective of this paper is to explain a new algorithm called Bus Regrouping Method to reduce coupling transitions. As a consequence the power dissipation due to the coupling capacitance or inter wire capacitance in deep sub-micron technology is optimized.
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