Bus Regrouping method to Optimize Power in DSM Technology

Abstract

In many digital processors, the power dissipation in apart [2,3]. In this method, the total number of transitions the bus is a major part of the total chip power dissipation. For occurring between the newly arrived data and the present CMOS circuits most power is dissipated as a dynamic power data on the bus is first calculated. If this number is more for charging and discharging node capacitances. In non deep than half the number of sub-micron technology, these capacitances are mainly the substrate capacitances of the bus wires where as in deep submicron technology inter wire capacitance also contribute to total capacitance. The main objective of this paper is to explain a new algorithm called Bus Regrouping Method to reduce coupling transitions. As a consequence the power dissipation due to the coupling capacitance or inter wire capacitance in deep sub-micron technology is optimized.

An Octo Coding Technique to Reduce Energy Transition in Low Power Vlsi Circuits

“…Such techniques are bus invert coding [1] is the best method to reduce the self transitions. Bus regrouping [18] DSM bus invert coding [7] low power bus coding techniques considering inter wire capacitance [2], portioned bus coding for energy reduction [9] methods are efficient methods to reduce the coupling transitions coding for minimizing energy in VLSI interconnect [6] and an efficient switching activity reduction technique for on -chip data bus methods reduce both self and coupling transitions. but most of the methods consider only one type of encoding technique to reduce power dissipation .while this paper considers both self and coupling transitional activities to reduce the power dissipation by octo-encoding technique in an on -chip data buses.…”