Fault tolerant structures for nanoscale gates

Martorell, F.; Cotofana, Sorin; Rubio, Antonio

doi:10.1109/nano.2007.4601264

Cited by 16 publications

(19 citation statements)

References 14 publications

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“…All the individual circuits should be evaluated. The initial populations are evaluated by the simple error function as illustrated in equation (4). After the evaluation of the initial populations, the individuals with the best fitness will be selected as the representations of their own populations.…”

Section: The Negatively-correlated Evolutionary Algorithm Descriptionmentioning

confidence: 99%

“…However, higher density also increases the electrical, manufacturing and reliability complexities of the integrated circuits [2]. The shrinking of the components near to the atomic scale increases the fault probability of the electronic devices [3] [4]. For electronic systems especially those working in harsh environments, reliability is the key.…”

Section: Introductionmentioning

confidence: 99%

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Negatively-correlated redundancy circuits evolution: A novel way of robust analog circuit synthesizing

Liu

Jiang

2010

Third International Workshop on Advanced Computational Intelligence

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Integrated circuit technology has been dramatically developed during the past decades. Reliability of analog circuits becomes more and more important for yield design. However, most state of the art researches are concentrated on analog circuit robust optimization and analog circuit fault detection. There are seldom any researches on analog circuit fault-tolerant design. This paper proposed an negativelycorrelated evolution strategy to design fault-tolerant analog circuits. In the proposed strategy, the fault-tolerant circuit can be considered as an ensemble system. The system contains several child circuits. negatively-correlated evolution strategy automatically synthesizes these child circuits, and make sure the errors of each child circuits are negatively correlated to each other. The experimental result shows that, in most circumstances, the circuit with negative correlation redundancy has the best fault tolerant performance compared with the circuit with randomly generated redundancy. The the circuit with duplicated redundancy didn't has much improvement compared with single circuit. So, the proposed strategy is a beneficial idea towards robust and fault tolerant analog circuit design.

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Section: The Negatively-correlated Evolutionary Algorithm Descriptionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Negatively-correlated redundancy circuits evolution: A novel way of robust analog circuit synthesizing

Liu

Jiang

2010

Third International Workshop on Advanced Computational Intelligence

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“…However, when taking into account the devices forming the gates, this result can change, e.g., it can reverse in certain cases when using single-electron technology [10]. Reliability analyses were made for NANDand MAJ-based multiplexing schemes with low and medium redundancy factors (3 to 3000), using various methods to compute or estimate the system reliability: analytical modelling [11], [12], [8], [9], [13], probability transfer matrix [14], [10], probabilistic model checking [15], [16], Monte Carlo simulations [10], [17] or Bayesian networks [18].…”

Section: Introductionmentioning

confidence: 99%

“…All of the above mentioned works consider that gates fail with the same probability, with the exception of [10], where the gates are implemented in Single-Electron Tunnelling (SET) technology, and [17], [18], where manufacturing variability effects on the multiplexing scheme are investigated. Our work also considers gates failing with different probabilities, but from a different perspective, and as an effect of a different Figure 2: Multiplexing unit reliability contribution in a highly faulty system.…”

Section: Introductionmentioning

confidence: 99%

Towards heterogenous 3D-stacked reliable computing with von Neumann multiplexing

Voicu

Cotofana

2013

2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

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The reliability of near-future nano-meter range CMOS, and novel nano-computing devices is greatly affected by undesired effects of physical phenomena appearing due to continuous technology scaling. The emerging 3D-Stacking Integrated Circuits (3D-SIC) technology allows devices manufactured using different technologies, and thus with different reliability, to be stacked on top of each other and connected with low latency links. In this paper, we propose to take advantage of this new design space dimension, i.e., the individual reliability of devices, when using the von Neumann multiplexing redundancy technique. Our analysis suggests that multiplexing units reliability importance is determined by how high the error rate of individual gates in the system is, i.e., for high error rates the units at the end of the restoration chain are critical, while for low error rates the units at the beginning of the restoration chain are critical. We further introduce and evaluate the first, to the best of our knowledge, heterogeneous 3D-SIC multiplexing arrangements. Our results indicate that assuming that delay and area are doubled for a technology with an order of magnitude higher reliability, a heterogeneous multiplexing scheme with gates having high and medium error rates can achieve a reduction of 1.79× in delay and area, with a 9% loss in the Reliability Improvement Index (RII), over the homogeneous counterpart with only medium reliability gates. For medium and low error rates, a minimum 1% RII loss can be traded for a delay and footprint reduction of 5.66× and 4.25×, respectively.

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“…A potential alternative to majority gates is the averaging (AVG) cell [7]- [9], which exhibits higher reliability at lower cost by computing the average of the input replicas instead of relying on majority voting. Moreover, as suggested in previous paper [10], for high fault rates AVG requires a reasonable redundancy level, thus area overhead, when compared with modular redundancy (MR) or NAND multiplexing. Working with the averaging technique variations in opposite directions can be compensated and thus reduce the output probability of error.…”

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confidence: 99%

Controlled Degradation Stochastic Resonance in Adaptive Averaging Cell-Based Architectures

Aymerich

Cotofana

Rubio

2013

IEEE Trans. Nanotechnology

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In this paper, we first analyze the degradation stochastic resonance (DSR) effect in the context of adaptive averaging (AD-AVG) architectures. The AD-AVG is the adaptive version of the well-known AVG architecture . It is an optimized fault-tolerant design for future technologies with very high rates of failures and defects. With system degradation the AD-AVG reliability is diminishing, as expected, but at a certain moment in time it increases due to the DSR occurrence, which is counterintuitive. We study this phenomenon under various redundancy levels and noise condition. If we take for example a 20-input AD-AVG with particular noise conditions, our simulations indicate an initial yield decrease from 1 to 0.89 with the system degradation, then a grow up to 0.94 at the DSR peak, and finally a decrease to zero when the system is reaching its end of life. Subsequently, we introduce a method to induce DSR in an AD-AVG structure, regardless of the degradation level, when this results in reliability improvement. To achieve this, we augment the AD-AVG with per input controllable noise injectors that can be utilized to induce virtual circuit degradation and create the required conditions for the DSR peak appearance. With this scheme the beneficial DSR effect is created even though the actual DSR system degradation (aging conditions) is not reached. This allows us to provide an optimum and nearly flat reliability level at any time before the DSR peak degradation level. Our experiments suggest that when we apply this method to the same 20-input AD-AVG, we obtain a guaranteed yield level of 0.94 from fresh devices to the DSR peak degradation level with a maximum yield of 0.97. In this way, a minimum yield level can be guaranteed, by determining at design time the required AD-AVG redundancy that provides it, for the entire life of the system.

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Fault tolerant structures for nanoscale gates

Cited by 16 publications

References 14 publications

Negatively-correlated redundancy circuits evolution: A novel way of robust analog circuit synthesizing

Negatively-correlated redundancy circuits evolution: A novel way of robust analog circuit synthesizing

Towards heterogenous 3D-stacked reliable computing with von Neumann multiplexing

Controlled Degradation Stochastic Resonance in Adaptive Averaging Cell-Based Architectures

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