Fault tolerance for arithmetic and logic unit

Abstract

Very large scale integration (VLSI) technology has evolved to a level where large systems, previously implemented as printed circuit boards with discrete components, are integrated into a single integrated circuit (IC). But aggressive new chip design technologies frequently adversely affect chip reliability during functional operation. Reliability is of critical importance in situations where a computer malfunction could have catastrophic results. Reliability is used to describe systems in which it is not feasible to repair (as in computers on board satellites) or in which the computer is serving a critical function and cannot be lost even for the duration of a replacement (as insight control computers on an aircraft) or in which therepair is prohibitively expensive. The use of concurrent error detection scheme with order to achieve the high reliability requirement of modern computer systems is becoming an important design technique. The present paper describes implementation of error-detection mechanisms for detecting faults within the Arithmetic Logic Unit (ALU). The Boolean unit of the ALU uses duplication of hardware with comparison as the error detection mechanism. The arithmetic unit of the ALU uses residue codes as the error detection mechanisms. If a fault is detected in the ALU we have to replace it with the spare ALU which will make error correction possible. We will compare this fault tolerance mechanism with the current fault-tolerance mechanisms (Triple redundancy with single voting scheme and Triple modular redundancy with triplicated voting mechanism).

Fault Tolerant ALU using Parity Preserving Reversible Logic Gates

“…The most stringent requirement for fault tolerant ALU is in real time control system where faulty computation jeopardizes human life or other catastrophic effects [10]. Section IV describes methodology for proposed fault tolerant ALU.…”

A Low Cost circuit level fault detection technique to Full Adder design

“…In [9] [10], authors have concluded that hardware redundancy techniques are very costly and improper for small arithmetic circuits. Consequently, they have exploited information redundancy methods, instead.…”

“…However, these techniques do not guarantee the detection of all errors. In [9] after comparison of different fault tolerant techniques, such as time redundancy or information redundancy, the authors have concluded that none of these methods alone, could protect arithmetic circuits. In addition, use of hardware redundancy would be very costly.…”

Redundancy Based Design and Analysis of ALU Circuit Using CMOS 180nm Process Technology for Fault Tolerant Computing Architectures

“…In the past few years, the design of computing architectures and circuits has become remarkably complex and dense, while the role and importance of the systems have increased explosively [1,2]. As the scale of integration increased from small/medium to large and to today's very large scale, the reliability per fundamental computing function require dramatic improvements.…”

“…As the demand of enhanced functionality is increasing, the complexity of systems has increased and that has raised the probability of complete failure of system. Moreover, our dependence on computing systems has grown to an extent that it has became impossible to return to less sophisticated mechanisms [1]. High reliability and uninterrupted operations in computing systems are much more vital in certain applications such as spacecraft navigation, aircraft flight control and landing systems, nuclear power plants, and chemical industries.…”