Redundancy Based Design and Analysis of ALU Circuit Using CMOS 180nm Process Technology for Fault Tolerant Computing Architectures

Singh, Tejinder; Pashaie, Farzaneh; Kumar, Rajat

doi:10.12785/ijcds/040106

Cited by 7 publications

(3 citation statements)

References 8 publications

(17 reference statements)

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“…The reliability for the combinational circuit R ckt is the function of gate reliability and the input signal probability from (3). Circuit's PTM is defined as the function of reliability and the input signal probability matrix is defined above in (7).…”

Section: B Illustration Of Ptm Algorithm For the Evaluation And Analmentioning

confidence: 99%

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Analysis of Reliability for the Gate Level Fault Tolerant Design using Probabilistic Transfer Matrix method

Dixit¹

2017

IJCDS

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Abstract:As semiconductor integrated circuits entered into nanometer dimensions, large variations of parameters and drastic reduction in reliability conditions of the constituent devices may be expected. On basis of these unreliable concerns, the research in fault analysis and development of fault tolerant design methodologies are the growing concern nowadays. Design and development of the fault tolerant model of the system/circuit include two major areas. First, types of fault and the level of fault occurrence at the input and output of the circuit. Second, the analysis of reliability for the logic circuit. The aim of this paper is to improve the reliability and fault tolerance level of the logic circuit by introducing gate level redundancy with respect to the occurrence of transient fault. Triple Modular Redundancy methodology is used to design the fault tolerant model that improves the reliability of the logic circuit. The proposed Probability Transfer Matrix (PTM) algorithm evaluates and compares the reliability of the logic circuit without redundancy and with redundancy by the analytical formulations. The results of circuit reliability with respect to the gate error probability has been simulated for the occurrence of transient faults for the proposed logic circuits. The results have shown better improvement in reliability and fault tolerance level of 0.7% for the proposed logic circuit using gate level redundancy.

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Section: B Illustration Of Ptm Algorithm For the Evaluation And Analmentioning

confidence: 99%

“…Tejinder singh et.al [7] designed and analysed the 4-bit Arithmetic and Logic Unit (ALU) circuit using CMOS 180nm process technology for fault tolerant computing structures. They used the fault tolerant technique known as Triple Modular Redundancy (TMR) to tolerate the manufacturing defects which achieves higher reliability.…”

Section: Introductionmentioning

confidence: 99%

Analysis of Reliability for the Gate Level Fault Tolerant Design using Probabilistic Transfer Matrix method

Dixit¹

2017

IJCDS

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“…Authors in [11] and [12] implemented basic logic gates and 4-bit Ripple Carry Adder using two-phase clocked adiabatic static CMOS logic (2PASCL). In [17] and [18] two adiabatic techniques based on bootstrapping logic is discussed.…”

Section: Introductionmentioning

confidence: 99%

Power dissipation reduction using adiabatic logic techniques for CMOS inverter circuit

Pindoo

Singhy

Singh

et al. 2015

2015 6th International Conference on Computing, Communication and Networking Technologies (ICCCNT)

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Power dissipation in circuits and systems is the critical factor for most of the researchers and industries. Many power dissipation techniques have been proposed but most of these techniques have some tradeoffs. Adiabatic logic technique in contrary to that of a conventional CMOS technique shows promising results. A variable supply voltage is provided instead of a constant supply required for CMOS logic. In this paper, an unconventional approach for reducing the power dissipation is reviews and implemented. Various techniques used for implementing adiabatic logic circuits are also discussed in this paper. The adiabatic CMOS and the conventional CMOS techniques are compared with respect to their power dissipation parameter. The simulation results obtained verifies that the circuits implemented using adiabatic logic approach dissipate lesser power compared to that of conventional static CMOS approach.

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Immunity to Radiation-Induced Faults

Popa

2022

The Read-Out Controller ASIC for the ATLAS Experiment at LHC

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Redundancy Based Design and Analysis of ALU Circuit Using CMOS 180nm Process Technology for Fault Tolerant Computing Architectures

Cited by 7 publications

References 8 publications

Analysis of Reliability for the Gate Level Fault Tolerant Design using Probabilistic Transfer Matrix method

Analysis of Reliability for the Gate Level Fault Tolerant Design using Probabilistic Transfer Matrix method

Power dissipation reduction using adiabatic logic techniques for CMOS inverter circuit

Immunity to Radiation-Induced Faults

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