Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems

Abstract

Abstract-This paper presents an analysis of the fault tolerance achieved by an autonomous, fully embedded evolvable hardware system, which uses a combination of partial dynamic reconfiguration and an evolutionary algorithm (EA). It demonstrates that the system may self-recover from both transient and cumulative permanent faults. This self-adaptive system, based on a 2D array of 16 (4×4) Processing Elements (PEs), is tested with an image filtering application. Results show that it may properly recover from faults in up to 3 PEs, that is, more than 18% cumulative permanent faults. Two fault models are used for testing purposes, at PE and CLB levels. Two self-healing strategies are also introduced, depending on whether fault diagnosis is available or not. They are based on scrubbing, fitness evaluation, dynamic partial reconfiguration and in-system evolutionary adaptation. Since most of these adaptability features are already available on the system for its normal operation, resource cost for self-healing is very low (only some code additions in the internal microprocessor core).

A scalable evolvable hardware processing array

“…Also an evolutionary strategy has been proposed, based on the concept of development, which obtains better results by evolving sequentially the system from one size to a bigger one. But there are more parameters to analyze, such as the complexity of the task, for instance with more noisy input images, and the fault tolerance of the system, that was explored in [16] for the case of the non-scalable architecture, and now it is expected to be enhanced due to the extra degree of freedom introduced. Another trend to work in is the integration of the scalable array with the multiple processing arrays system presented in [15], obtaining a fully scalable architecture, and also the development of the proper evolutionary algorithm in charge of deciding when it is needed to scale, and how to do it, whether increasing the number of processing arrays or the size of one of them.…”

A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays

“…This has been analyzed in [5], [10] and [11], in combination with EHW. Apart from using the EA as a method for finding an optimized solution to solve a problem, this technique works as a self-healing technique because faulty designs are treated as sub-optimal solutions in the evolution, and therefore they are discarded in favor of a better solution, so the fault is avoided, or healed.…”

“…Evolution is in charge of deciding which PE is reconfigured in each position of the array, until obtaining the desired functionality. Basic self-healing properties of this system were reported in [5].…”

Scalable FPGA Refurbishment Using Netlist-Driven Evolutionary Algorithms

“…A complete implementation of an EH system on a Xilinx Virtex-5 FPGA chip is demonstrated in [14]; composed of a 2D array of 16 Processing Elements (PEs) for computation on the reconfigurable logic and the evolutionary algorithm as a tool for self-recovery on the embedded microprocessor with the ability to internally reconfigure the PEs through Internal Configuration Access Port (ICAP) [28]. Fault tolerance experiments with an image filtering application indicates recovery time from hard failure, of less than a minute on this platform.…”

“…An alternative is to recompute the mapping and placement & routing operations on the affected partial FPGA configuration in the field via CAD algorithms [32], but this is a computationally expensive operation. On the other hand, the reconfiguration algorithm proposed herein is readily implementable with low area overhead in custom hardware or on an embedded microprocessor [14], [33]. For example, [33] reports logic utilization of just 13% and memory utilization of only 1% on a relatively small Virtex II-Pro FPGA device and achieves around 5.16x speedup over analogous software…”